• DocumentCode
    996560
  • Title

    New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement

  • Author

    Huang, Wei Kang ; Shen, Yi-Nan ; Lombardi, Fabtrizio

  • Author_Institution
    Dept. of Electr. Eng., Fudan Univ., China
  • Volume
    9
  • Issue
    3
  • fYear
    1990
  • fDate
    3/1/1990 12:00:00 AM
  • Firstpage
    323
  • Lastpage
    328
  • Abstract
    Two approaches for the repair of large random access memory (RAM) devices in which redundant rows and columns are added as spares are presented. These devices, referred to as redundant RAMs, are repaired to achieve acceptable yield at manufacturing and production times. The first approach, the faulty line covering technique, is a refinement of the fault-driven approach. This approach finds the optimal repair solution within a smaller number of iterations than the fault-driven algorithm. The second approach exploits a heuristic criterion in the generation of the repair solution. This heuristic criterion permits a fast repair. The criterion is based on the calculation of efficient coefficients for the rows and columns of the memory. Simulation results are presented. Comparison of the proposed heuristic approaches with the fully exhaustive approach shows that repair can be accomplished in most cases. A considerable reduction in processing and complexity (number of records generated in the repair process for finding the optimal repair solution) is accomplished
  • Keywords
    VLSI; circuit reliability; fault location; integrated memory circuits; random-access storage; redundancy; VLSI; complexity reduction; efficient coefficients; fault-driven algorithm; faulty line covering technique; heuristic criterion; large RAM devices; memory repair; optimal repair solution; processing reduction; random access memory; redundancy; redundant RAMs; redundant rows; row/column deletion; yield enhancement; Costs; Counting circuits; Manufacturing; Production; Random access memory; Read-write memory; Redundancy; Refining; Very large scale integration; Wafer scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.46807
  • Filename
    46807