Title :
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Author :
Lin, Jai-Ming ; Chang, Yao-Wen
Author_Institution :
Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
6/1/2004 12:00:00 AM
Abstract :
In this paper, we extend the concept of the P-admissible floorplan representation to that of the P*-admissible one. A P*-admissible representation can model the most general floorplans. Each of the currently existing P*-admissible representations, sequence pair (SP), bounded-slicing grid, and transitive closure graph (TCG), has its strengths as well as weaknesses. We show the equivalence of the two most promising P*-admissible representations, TCG and SP, and integrate TCG with a packing sequence (part of SP) into a representation, called TCG-S. TCG-S combines the advantages of SP and TCG and at the same time eliminates their disadvantages. With the property of SP, a fast packing scheme is possible. Inherited nice properties from TCG, the geometric relations among modules are transparent to TCG-S (implying faster convergence to a desired solution), placement with position constraints becomes much easier, and incremental update for cost evaluation can be realized. These nice properties make TCG-S a superior representation which exhibits an elegant solution structure to facilitate the search for a desired floorplan/placement. Extensive experiments show that TCG-S results in the best area utilization, wirelength optimization, convergence speed, and stability among existing works and is very flexible in handling placement with special constraints.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; graph theory; integrated circuit interconnections; integrated circuit layout; network routing; P*-admissible representations; P-admissible floorplan representation; area utilization; bounded-slicing grid; convergence speed; fast packing scheme; general floorplans; geometric module relations; orthogonal coupling; packing sequence; physical design; placement; position constraints; sequence pair; transitive closure graph; wirelength optimization; Circuit stability; Constraint optimization; Costs; Design optimization; Performance evaluation; Polynomials; Solid modeling; Timing; Tree graphs; Very large scale integration; Floorplanning; layout; physical_design; transitive_closure_graph;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2004.828114