Title :
Low-temperature f.e.t. for low-power high-speed logic
Author :
Rees, H. ; Sanghera, G.S. ; Warriner, R.A.
Author_Institution :
RSRE, Malvern, UK
Abstract :
A novel f.e.t. cooled to around 100 K is proposed. Detailed computer simulations support the conjecture of high-speed switching at low power levels with a power-delay product ¿ 10¿14 J.
Keywords :
digital simulation; field effect transistors; logic devices; 100K; computer simulations; high speed switching; low power high speed logic; low temperature FET; power delay product;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19770111
