Title :
Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits
Author :
Chakravarty, S. ; Ravi, S.S.
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
fDate :
3/1/1990 12:00:00 AM
Abstract :
A sequence of input vectors which detects all transistor stuck-open faults in a CMOS combinational circuit is a complete test sequence. Given a complete set of two-pattern tests for transistor stuck-open faults in a CMOS circuit, it is shown that a complete test sequence of minimum length can be obtained efficiently. A precise description of this problem and examples to illustrate the method are presented
Keywords :
CMOS integrated circuits; combinatorial circuits; integrated logic circuits; logic testing; CMOS circuits; combinational circuit; complete test sets; input vector sequence; logic testing; minimum length; optimal test sequences; stuck-open faults; two-pattern tests; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Computer science; Design automation; Electrical fault detection; Fault detection; Robustness; Semiconductor device modeling;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
