Domain Crossing Errors: Limitations on Single Device Triple-Modular Redundancy Circuits in Xilinx FPGAs

Author

Quinn, Heather ; Morgan, Keith ; Graham, Paul ; Krone, Jim ; Caffrey, Michael ; Lundgreen, Kevin

Author_Institution

Los Alamos Nat. Lab., Los Alamos

Volume

54

Issue

6

fYear

2007

Firstpage

2037

Lastpage

2043

Abstract

This paper discusses the limitations of single-FPGA triple-modular redundancy in the presence of multiple-bit upsets on Xilinx Virtex-II devices. This paper presents results from both fault injection and accelerated testing. From this study we have found that the configurable logic block´s routing network is vulnerable to domain crossing errors, or TMR defeats, by even 2-bit multiple-bit upsets.

Keywords

aerospace instrumentation; field programmable gate arrays; proton effects; Xilinx FPGA; Xilinx Virtex-II devices; accelerated testing; configurable logic block routing network; domain crossing errors; fault injection; fault tolerance; field programmable gate arrays; hardness measurement; multiple-bit upsets; proton radiation effects; radiation hardening; redundant systems; single device triple-modular redundancy circuits; single-FPGA triple-modular redundancy; Circuit faults; Circuit testing; Costs; Field programmable gate arrays; Hardware; Laboratories; Life estimation; Logic programming; Random access memory; Redundancy; Fault tolerance; field programmable gate arrays; hardness measurement; proton radiation effects; radiation hardening; redundant systems;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2007.910870

Filename

4395073