Title :
Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique
Author :
Cho, Won-Ju ; Ahn, Chang-Geun ; Im, Kiju ; Yang, Jong-Heon ; Oh, Jihun ; Baek, In-Bok ; Lee, Seongjae
Author_Institution :
Semicond. Basic Res. Lab., ETRI, Daejeon, South Korea
fDate :
6/1/2004 12:00:00 AM
Abstract :
A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 Ω/□ by the elevated temperature plasma doping of 527 °C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.
Keywords :
MOSFET; nanoelectronics; semiconductor doping; silicon-on-insulator; 50 nm; 527 C; SOI n-MOSFET; abrupt S/D junction; activation annealing; dopant diffusion; elevated temperature plasma-doping method; gate length; sheet resistance; short-channel effects; silicon-on-insulator; source/drain extensions; tri-gate structure; Annealing; Doping; Fabrication; Ion implantation; Lithography; MOSFET circuits; Plasma immersion ion implantation; Plasma sources; Plasma temperature; Silicon on insulator technology; Elevated temperature; MOSFETs; SOI; low damage; nanoscale; plasma doping; silicon-on-insulator; tri-gate structure;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2004.829007
