Title :
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme
Author :
Yamaoka, Masanao ; Osada, Kenichi ; Ishibashi, Koichiro
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
6/1/2004 12:00:00 AM
Abstract :
We designed a logic-library-friendly SRAM array. The array uses rectangular-diffusion cell (RD cell) and delta-boosted-array-voltage scheme (DBA scheme). In the RD cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA scheme compensates it. Using the combination of RD cell and DBA scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency, 140-μW power dissipation, and 0.9-μA standby current.
Keywords :
CMOS memory circuits; SRAM chips; logic design; low-power electronics; 0.4 V; 0.9 muA; 140 muW; 4.5 MHz; cell ratio; delta-boosted-array voltage scheme; logic-library-friendly SRAM array; low supply voltage; power dissipation; rectangular-diffusion cell; standby current; static noise margin; Circuit testing; Fabrication; Fluctuations; Frequency; Logic arrays; Logic circuits; Low voltage; MOS devices; Random access memory; Shape; 0.4-V operation; DBA; RD; SRAM; cell; delta-boosted-array; rectangular-diffusion; scheme;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.827796
