• DocumentCode
    997549
  • Title

    Implementation of wireless LAN baseband processor based on space-frequency OFDM transmit diversity scheme

  • Author

    Jung, Yunho ; Noh, Seungpyo ; Yoon, Hongil ; Kim, Jaeseok

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
  • Volume
    51
  • Issue
    2
  • fYear
    2005
  • fDate
    5/1/2005 12:00:00 AM
  • Firstpage
    393
  • Lastpage
    398
  • Abstract
    In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM wireless LAN (WLAN) baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers is generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at BER=10-4 the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at 80% of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18 μm 1.8 V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945 K. The real-time operation is verified and evaluated using a FPGA test system.
  • Keywords
    CMOS logic circuits; OFDM modulation; diversity reception; error statistics; field programmable gate arrays; hardware description languages; interference suppression; radio links; radiofrequency interference; receiving antennas; signal detection; transmitting antennas; wireless LAN; 0.18 mum; 1.8 V; 3 dB; 5.95 dB; BER performance; FPGA test system; bit error rate; gate-level circuit; packet error rate; receive antenna; space-frequency OFDM transmit diversity scheme; symbol detection algorithm; transmit antenna; wireless LAN baseband processor; Baseband; Bit error rate; Detection algorithms; Gain; Interference elimination; Logic testing; OFDM; Receiving antennas; Throughput; Wireless LAN;
  • fLanguage
    English
  • Journal_Title
    Consumer Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-3063
  • Type

    jour

  • DOI
    10.1109/TCE.2005.1467977
  • Filename
    1467977