An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates

The predicted deterioration of the component quality, due to the shrinking of components to near atomic scale, threatens the effectiveness and the applicability of conventional digital system design methodologies in the giga and tera-scale integration era. Three aggression sources support the previous statement: i) the increasing device parameter variability induced by the extreme reduction of the critical feature sizes and the intrinsic nature of new devices; ii) the intense and practically unpredictable internal noise; and iii) the large number of physical defects. This paper provides a detailed analysis of the noise and parameter variations effects on a basic processing gate. We derive formulas to calculate the expected value and the variance of the gate output under the effects of noise, threshold, and gain fluctuations. Using these expressions we also derive a cost-performance equation that evaluates the gate error probability from its parameter variability, noise, power, and area or redundance. The proposed model is generic for any computing gate in the current digital paradigm. To illustrate the model applicability we calculate the error probability curve for a 90 nm CMOS inverter showing that for this technology the noise is the main limiting factor. A tradeoff analysis of area-power-redundancy-reliability for nanogates is performed indicating that the use of nanoscale individual elements for fabricating gates in deep-nanoscale technologies may not be a viable option. The results clearly suggest that the use of redundant structures is necessary and that averaging structures with mid-high redundancy factors may constitute a reasonable solution for building reliable nanoscale gates.