Title :
LORES-2: A Logic Reorganization System
Author :
Enomoto, Kiyoshi ; Nakamura, Shunichiro ; Ogihara, Takuji ; Murai, Shinichi
Author_Institution :
Mitsubishi Electric Corporation
Abstract :
LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.
Keywords :
Circuit simulation; Circuit synthesis; Databases; Large scale integration; Logic circuits; Logic design; Logic testing; Programmable logic arrays; Read only memory; Synthesizers;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.1985.294814