Generating single-stuck-fault coverage from a collapsed-fault set

Author

Heap, Mark A. ; Rogers, William A.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

Volume

22

Issue

4

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

51

Lastpage

57

Abstract

Fault simulators do not simulate all the single stuck faults (SSFs), because as the simulated fault set grows, the increase in their runtime and memory requirements is greater than linear. Fault-set size is reduced, or collapsed, during circuit preprocessing by using the concepts of equivalence and dominance. It is shown that collapsed-fault (CF) coverage is not the same as SSF coverage and that this difference has a large effect on the defect level as the coverage approaches 100%. A very-low-overhead technique is presented that calculates true fault coverage while simulating with a CF set, thereby retaining the runtime and memory savings of simulating with CFs without sacrificing fault-coverage accuracy. This technique can be applied to any fault model exhibiting equivalence and dominance properties. The results are confirmed by benchmark results.<>

Keywords

circuit analysis computing; integrated circuit testing; integrated logic circuits; logic testing; benchmark results; circuit preprocessing; collapsed-fault set; dominance; equivalence; fault coverage; single-stuck-fault coverage; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Impedance matching; Logic circuits; Manufacturing; Predictive models; Runtime; Statistical analysis;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.25382

Filename

25382