عنوان مقاله :
An efficient parallel critical path tracing for path delay fault simulation
پديد آورندگان :
Sabaghian-Bidgoli ، Hossein University of Kashan - Department of Computer Engineering , Ehteram ، Ahmad Kashan Branch Islamic Azad University - Department of Electrical Engineering , Ghasvari ، Hossein Kashan Branch Islamic Azad University - Department of Electrical Engineering , Delshad ، Majid Isfahan (Khorasgan) Branch Islamic Azad University - Department of Electrical Engineering , Hessabi ، Shaahin Sharif University of Technology - Department of Computer Engineering
كليدواژه :
Path delay fault , Fault simulation , Critical path tracing , Robust path , Non , robust path
چكيده فارسي :
Delay fault simulation is the most general method that is used to assess the quality of generated test sets. Path delay fault is one of the most frequently used delay fault models. Path delay fault simulation is a time-consuming operation, especially for today’s complex digital circuits. In this work, a novel critical path tracing algorithm is proposed for parallel path delay fault simulation. The obtained outcomes denote 489 times average speedup compared with the traditional path tracing, as well as 186 times average speed-up in comparison with the latest reported results of previous studies.
عنوان نشريه :
محاسبات نرم
عنوان نشريه :
محاسبات نرم
