عنوان مقاله :
طراحي مدولاتورهاي سيگما - دلتا با سرعت بالا و ولتاژ بسيار پايين
عنوان به زبان ديگر :
Design Of Very Low-Voltage High-Speed Sigma-Delta Modulators
پديد آورندگان :
ياوري، محمدف شعاعي نويسنده ,
اطلاعات موجودي :
دو ماهنامه سال 1383 شماره 85
رتبه نشريه :
فاقد درجه علمي
كليدواژه :
طراحي مدولاتورهاي سيگما - دلتا , مبدل هاي سيگما دلتا , مدولاتورها , تقويت كننده هاي عملياتي , مهندسي برق , تغذيه مدارهاي ديجيتال , ولتاژ , Low-Voltage , مدارهاي آنالوگ , Sigma-Delta , CMOS مقايسه گرهاي , High-Speed , DAC خطي سازي , ADCs , كونتايزرهاي چند بيتي , Modulators , HSPICE
چكيده لاتين :
Demands for low voltage power supply in mixed-signal designs are growing due to portable equipment capable of operating with minimum number of battery cells to
reduce volume and weight with longer operating periods and also voltage limitations resulted from smaller feature sizes of modem IC technologies. Also with the recent developments in both wired and wireless communications, there is a need to design analog-to-digital converters (ADCs) at MHz speeds with high linearity.
Sigma-delta modulators and pipelined ADCs are the two main candidates for high-resolution and high-speed applications. Pipelined converters need some type of calibration or error correction techniques to achieve accuracies beyond 12-bits, resulting in increased complexity and power dissipation. Some sigma-delta ADCs have been reported in the MHz ranges with resolutions about 14-bits and beyond. In this paper a novel sigma-delta modulator architecture suitable for very low-voltage and high-resolution in the MHz ranges is proposed. The main specifications of the proposed architecture are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal-to-noise ratio (SNR) with a low oversampling ratio (OSR), and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections.
The implemented prototype of the proposed modulator architecture with HSPICE gives SNDR and dynamic range of 90-dB and 92.5-dB, respectively, including the circuit noise with a single power supply voltage of 1.2-V. The circuit requirements for implementation of the modulator were simulated in a 0.13um CMOS technology. A new class AIAB operational transconductance amplifier with cascode compensation was proposed to implement the integrators, BR filter, and gain-stage. The signal bandwidth and sampling frequency are 1.25 MHz and 40 MHz, respectively. The total power dissipation was about 40-mW.
عنوان نشريه :
نشريه دانشكده فني دانشگاه تهران
عنوان نشريه :
نشريه دانشكده فني دانشگاه تهران
اطلاعات موجودي :
دوماهنامه با شماره پیاپی 85 سال 1383
كلمات كليدي :
#تست#آزمون###امتحان