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Hardware implementation of FIR filter
2
Hardware implementation of FM multipath distortion canceller
3
Hardware implementation of four-step genetic search algorithm
4
Hardware implementation of free division block-based BSS algorithm
5
Hardware implementation of Frequency Domain Link Adaptation for OFDMA based systems
6
Hardware implementation of fuzzy filtering
7
Hardware implementation of fuzzy logic based maximum power point tracking controller for PV systems
8
Hardware implementation of fuzzy logic controller
9
Hardware implementation of fuzzy logic MPPT controller on a FPGA platform
10
Hardware implementation of fuzzy Petri net as a controller
11
Hardware implementation of fuzzy systems
12
Hardware implementation of fuzzy-PI-sliding mode speed controller of induction motors
13
Hardware implementation of GCFD for color images recognition
14
Hardware implementation of GCPVS using isolated Cuk converter
15
Hardware implementation of generalized profile search on the GENSTORM machine
16
Hardware implementation of genetic algorithm modules for intelligent systems
17
Hardware implementation of genetic algorithm on FPGA
18
Hardware implementation of genetic algorithms using FPGA
19
Hardware implementation of GMDH-type artificial neural networks and its use to predict approximate three-dimensional structures of proteins
20
Hardware implementation of GPRS enabled embedded server for remote access terminal
21
Hardware implementation of Grain-128, Mickey-128, Decim-128 and Trivium
22
Hardware implementation of grid connected PV system with energy management scheme
23
Hardware implementation of grid connected transformer-less semi-Z-source inverter topology to mitigate common mode leakage current and THD
24
Hardware implementation of ground classification for a walking robot
25
Hardware implementation of habituation
26
Hardware Implementation of Hash Function SHA-512
27
Hardware implementation of HEVC CABAC encoder
28
Hardware Implementation of Hierarchical Volume Subdivision-based Elastic Registration
29
Hardware implementation of high efficient and high voltage gain dc-dc converter for dc microgrid applications
30
Hardware Implementation of High Throughput RC4 algorithm
31
Hardware implementation of IC-PCNN for the color image segmentation
32
Hardware implementation of IIR digital filters for programmable devices
33
Hardware Implementation of Image Space Reconstruction Algorithm using FPGAs
34
Hardware Implementation of Improved Montgomery Modular Multiplication Algorithm
35
Hardware implementation of interval type-2 fuzzy logic controller
36
Hardware implementation of Iris recognition algorithm
37
Hardware implementation of JPEG2000 encoder for video compression
38
Hardware implementation of key functionalities of NIPS for high speed network
39
Hardware implementation of KLMS algorithm using FPGA
40
Hardware implementation of Kuiper-based modulation level classification
41
Hardware Implementation of k-Winner-Take-All Neural Network with On-chip Learning
42
Hardware implementation of large number multiplication by FFT with modular arithmetic
43
Hardware implementation of lifting based wavelet transform
44
Hardware implementation of linear back-projection algorithm for capacitance tomography
45
Hardware implementation of link aggregation in networks-on-chip
46
Hardware implementation of Log-MAP turbo decoder for W-CDMA Node B with CRC-aided early stopping
47
Hardware Implementation of Lossless Adaptive and Scalable Hyperspectral Data Compression for Space
48
Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking
49
Hardware implementation of low-overhead data aided timing and Carrier Frequency Offset correction for OFDM signals
50
Hardware implementation of LU decomposition using dataflow architecture on FPGA
51
Hardware implementation of mapper for faster-than-Nyquist signaling transmitter
52
Hardware Implementation of Math Module Based on CORDIC Algorithm Using FPGA
53
Hardware implementation of matrix inversion for Raptor decoder on embedded system
54
Hardware implementation of maximum Lyapunov exponent
55
Hardware implementation of Max-Log-MAP algorithm based on MacLaurin series for turbo decoder
56
Hardware implementation of MFCC feature extraction for respiratory sounds analysis
57
Hardware implementation of microarray image segmentation
58
Hardware implementation of Model Predictive Control for relative motion maneuvering
59
Hardware implementation of montgomery modular multiplication algorithm using iterative architecture
60
Hardware implementation of Montgomery´s modular multiplication algorithm
61
Hardware implementation of Moore test on FPGA
62
Hardware implementation of motion blur removal
63
Hardware implementation of motion estimation using a sub-sampled block for frame rate up-conversion
64
Hardware implementation of MPEG analysis and deblocking for video enhancement
65
Hardware implementation of MPI_Barrier on an FPGA cluster
66
Hardware implementation of MRF map inference on an FPGA platform
67
Hardware Implementation of muC/OS-II Based on FPGA
68
Hardware implementation of multimedia driven HFC MAC protocol
69
Hardware Implementation of MUSIC Algorithm for Airborne Digital Direction Finding System
70
Hardware Implementation of MUSIC and ESPRIT on NI-PXI Platform
71
Hardware Implementation of Nakagami and Weibull Variate Generators
72
Hardware implementation of NB PHY baseband transceiver for IEEE 802.15.6 WBAN
73
Hardware implementation of negative selection algorithm for malware detection
74
Hardware implementation of neural network controlled optimal PWM inverter using TMS320C30 board
75
Hardware implementation of neural network on FPGA for accidents diagnosis of the multi-purpose research reactor of Egypt
76
Hardware implementation of neural network with expansible and reconfigurable architecture
77
Hardware implementation of Neural-Fuzzy Network based image denoising approximation
78
Hardware implementation of neuro-fuzzy system with the analogue-digital hybrid neural chip
79
Hardware implementation of nonlinear PID controller with FPGA based on floating point operation for 6-DOF manipulator robot arm
80
Hardware implementation of novel image compression-encryption system on a FPGA
81
Hardware implementation of OFDM transceiver using FPGA
82
Hardware implementation of optimal CALLUM transmitter
83
Hardware implementation of optimization technique based sensorless MPPT method for grid-connected PV generation system
84
Hardware Implementation of P Systems Using Microcontrollers. An Operating Environment for Implementing a Partially Parallel Distributed Architecture
85
Hardware implementation of packet-fair queuing schedulers in high speed networks
86
Hardware implementation of PAPR reduction scheme for OFDM system
87
Hardware implementation of parallel processors in fuzzy processing control
88
Hardware implementation of post-retinal processing using analog VLSI
89
Hardware implementation of pragmatic Trellis Coded Modulation applied to 8PSK and 16QAM for DVB standard
90
Hardware Implementation of Prearranged Tables Based Modular Inversion
91
Hardware implementation of programmable cellular automata encryption algorithm
92
Hardware implementation of programmable coefficients recursive digital filter
93
Hardware implementation of programming languages for real-time
94
Hardware Implementation of Proposed Antenna Selection Algorithm and Its Performance Evaluation Using Received Signals in Field Experiment
95
Hardware implementation of pulse mode RBFNN based edge detection system on virtex V platform
96
Hardware implementation of quad microelectromechanical sensor structure for inertial systems
97
Hardware implementation of quasigroup based encryption
98
Hardware Implementation of Quasigroup Encryption for SCADA Networks
99
Hardware implementation of Radial Basis Function Neural Network based on sigma-delta modulation
100
Hardware implementation of RAM-based neural networks for tomographic data processing
101
Hardware Implementation of Rayleigh and Ricean Variate Generators
102
Hardware Implementation of Real Time Cavity Parameters Identification System
103
Hardware implementation of real-time multiple frame super-resolution
104
Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP
105
Hardware Implementation of Real-Time, High Performance, RCE-NN Based Face Recognition System
106
Hardware implementation of reception diversity techniques for spectrum sensing efficiency enhancement in cognitive radio network
107
Hardware implementation of Recurrent S_CMAC_GBF based on FPGA
108
Hardware implementation of recursive algorithms
109
Hardware implementation of recursive sorting algorithms
110
Hardware implementation of Reed-Solomon error correction technique for wireless sensor network based on error pattern analysis
111
Hardware implementation of remote laboratory for Digital Electronics
112
Hardware Implementation of RFID Mutual Authentication Protocol
113
Hardware implementation of robust constrained hearing aid arrays
114
Hardware Implementation of Secure Shamir´s Secret Sharing Scheme
115
Hardware implementation of sensorless SMPMSM drive for wide speeds using modified MRAS and DC link quantities based on dsPIC33E DSC
116
Hardware implementation of series hybrid active power filter using a novel control strategy based on generalised instantaneous power theory
117
Hardware implementation of session initiation protocol servers and clients
118
Hardware implementation of SHA-3 candidate based on BLAKE-32
119
Hardware implementation of shading models in an application specific integrated circuit
120
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank
121
Hardware implementation of shortened (48,38) Reed Solomon forward error correcting code
122
Hardware Implementation of Signal Perturbation Theory
123
Hardware implementation of simultaneous M mutually orthogonal complementary sets of sequences algorithms
124
Hardware implementation of single-phase Shunt Active Power Filter with hysteresis current control loop for rectifier type load
125
Hardware implementation of smooth region switching for wind turbine control using PDF controller
126
Hardware implementation of soft-decision decoding for Reed-Solomon code
127
Hardware implementation of software radios
128
Hardware implementation of solar tracking system using a stepper motor
129
Hardware implementation of some DBMS functions using SPR
130
Hardware implementation of space vector PWM control of Permanent Magnet Synchronous Motor
131
Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms
132
Hardware implementation of stereo correspondence algorithm for the ExoMars mission
133
Hardware implementation of stochastic-based Neural Networks
134
Hardware implementation of super minimum all digital FM demodulator
135
Hardware implementation of surface electromyogram signal processing: A survey
136
Hardware Implementation of SVD Based Colour Image Watermarking in Wavelet Domain
137
Hardware Implementation of Symbol Synchronization for Underwater FSK
138
Hardware implementation of the advanced SCAMP downlink processor
139
Hardware implementation of the backpropagation without multiplication
140
Hardware implementation of the binary method for exponentiation in GF(2m)
141
Hardware implementation of the bit interleaver for the IEEE 802.22 Standard
142
Hardware implementation of the current control using the internal model method in the Electric Power Steering application
143
Hardware implementation of the depth first search bit stream SPIHT system
144
Hardware implementation of the discrete fourier transform with non-power-of-two problem size
145
Hardware implementation of the double-tree scan architecture
146
Hardware implementation of the encoder modified mid-band exchange coefficient technique (MMBEC) based on FPGA
147
Hardware implementation of the exponential function using Taylor series
148
Hardware implementation of the FAPEC lossless data compressor for space
149
Hardware Implementation of the Fast Optimization Method eDEAS
150
Hardware implementation of the GPS authentication
151
Hardware Implementation of the High Frequency Link Inveter Using the dSPACE DS1104 Digital Signal Processing Board
152
Hardware implementation of the Hirschman Optimal Transform
153
Hardware implementation of the IDEA NXT crypto-algorithm
154
Hardware implementation of the improved trellis algorithm
155
Hardware implementation of the improved WEP and RC4 encryption algorithms for wireless terminals
156
Hardware implementation of the Lehmer random number generator
157
Hardware implementation of the median-rational hybrid filters
158
Hardware implementation of the neural gas
159
Hardware implementation of the optimized transform and quantization blocks of H.264
160
Hardware implementation of the PBAS foreground detection method in FPGA
161
Hardware implementation of the predictive inverse neurocontrol system using ARM7 embedded processor
162
Hardware implementation of the RC4 stream cipher
163
Hardware implementation of the real time neural network components
164
Hardware implementation of the Reed-Solomon decoder
165
Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system
166
Hardware Implementation of the Salsa20 and Phelix Stream Ciphers
167
Hardware implementation of the Smith-Waterman algorithm using a systolic architecture
168
Hardware implementation of the Smith-Waterman Algorithm using Recursive Variable Expansion
169
Hardware implementation of the space-time radio interferometric positioning system
170
Hardware implementation of the subdivision loop algorithm
171
Hardware implementation of the SUMIS detector using high-level synthesis
172
Hardware implementation of the Totally Self-Checking SHA-256 hash core
173
Hardware implementation of the wavelet transform coupled with Artificial Neural Network for quantification purposes
174
Hardware Implementation of Traffic Controller using Fuzzy Expert System
175
Hardware implementation of trained networks
176
Hardware implementation of transform and quantization for AVS encoder
177
Hardware implementation of trellis coded quantization
178
Hardware implementation of triangulation method based on CORDIC algorithm
179
Hardware implementation of triply selective Rayleigh fading channel simulators
180
Hardware implementation of truncated multiplier based on multiplexer using FPGA
181
Hardware implementation of Turbo coder in LTE system based on PICOCHIP PC203
182
Hardware implementation of two key equation solvers for Reed-Solomon decoding
183
Hardware Implementation of Two Key Equation Solvers for Reed-Solomon Decoding
184
Hardware implementation of two-dimensional digital filters using ROM.
185
Hardware implementation of type-2 programmable fuzzifier
186
Hardware implementation of ultralightweight cryptographic protocols
187
Hardware implementation of underwater acoustic localization system for bridge scour monitoring
188
Hardware implementation of variable precision multiplication on FPGA
189
Hardware implementation of variable pulse frequency algorithm
190
Hardware implementation of versatile zigzag-reordering algorithm for adaptive JPEG-like image compression schemes
191
Hardware implementation of visible watermarking
192
Hardware implementation of voice operated robot using Support Vector Machine classifier
193
Hardware implementation of wideband time domain Robust Capon Beamforming
194
Hardware implementation of windowing in a multicast packet switch
195
Hardware implementation on a Xilinx Virtex4
196
Hardware implementation on FPGA of two modulation techniques for three phase inverters
197
Hardware implementation on m parameter ML estimation of Nakagami-m fading channel
198
Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator
199
Hardware implementation perspectives of digital video watermarking algorithms
200
Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm
201
Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations
202
Hardware implementation versus software emulation of fuzzy algorithms in real applications
203
Hardware implementation with off-line test capabilities of the RC6 block cipher
204
Hardware implementations and performance assessments of a DC magnetron sputter for enhanced depositions
205
Hardware implementations for CNN (Cellular Neural Network)-based nonautonomous MLC circuit
206
Hardware implementations for digital filters with low coefficient sensitivity
207
Hardware implementations of algorithms on networks of FPGA processors
208
Hardware implementations of denormalized numbers
209
Hardware implementations of Elliptic Curve Cryptography in Wireless Sensor Networks
210
Hardware Implementations of Fixed-Point Atan2
211
Hardware implementations of Gaussian elimination over GF(2) for channel decoding algorithms
212
Hardware implementations of hash function Luffa
213
Hardware implementations of high-speed network monitors
214
Hardware implementations of inference mechanisms in expert systems using continuous logic
215
Hardware implementations of multi-layer feedforward neural networks and error backpropagation using 8-bit PIC microcontrollers
216
Hardware implementations of Swarming Intelligence — a survey
217
Hardware implementations of the data encryption standard
218
Hardware implementations of the SHA-3 candidates Shabal and CubeHash
219
Hardware implementations of the WG-5 cipher for passive RFID tags
220
Hardware implemented adaptive neuro fuzzy system
221
Hardware improvement of Cybernetic Human HRP-4C for entertainment use
222
Hardware in a loop-a system prototyping platform for MIMO-approaches
223
Hardware in loop implementation and analysis of a neural augmented fault tolerant flight controller for a high performance dynamic fighter aircraft model on a target digital signal processor
224
Hardware in loop methodologies for the control of dual-PMSM connected in parallel: FPGA implementation and experimentation
225
Hardware in loop simulation for vehicle controller in HEV based on dSPACE
226
Hardware in loop solar panel simulator for two axis stabilized pico-satellite
227
Hardware in loop testing of an insulin pump
228
Hardware in speech and signal processing
229
Hardware in the loop (HIL) generation of airborne clutter using a sum of complex sinusoids technique
230
Hardware in the Loop (HIL) test bench for small-scale Distributed Generation systems
231
Hardware in the loop (HILS) testing of a power electronics controller with RTDS
232
Hardware in the loop based synchronous generator emulation test rig for more electric aircraft power systems
233
Hardware in the loop emulation of synchronous generators for aircraft power systems
234
Hardware in the loop for automotive vehicle control systems development
235
Hardware in the loop for electronic speed limiter
236
Hardware in the loop for optical flow sensing in a robotic bee
237
Hardware In the Loop for VDM-real time modeling of embedded systems
238
Hardware in the Loop implementation of a disturbance based control in MVDC grids
239
Hardware in the loop implementation of linearizing state feedback on MVDC ship systems and the significance of longitudinal parameters
240
Hardware in the loop laboratory simulation to test a distributed avionic system
241
Hardware in the loop radar environment simulation on wideband DRFM platforms
242
Hardware in the loop simulation and Machine Modular Development: Concepts and application
243
Hardware in the loop simulation applied to semi-autonomous underwater vehicles
244
Hardware in the loop simulation for distributed automation systems
245
Hardware in the loop simulation for optimal management of electrical power converters
246
Hardware in the loop simulation for PIAGGIO MP3 control systems validation
247
Hardware in the loop simulation of a dielectric elastomer generator for oscillating water column wave energy converters
248
Hardware In the Loop Simulation of a Diesel Parallel Mild-Hybrid Electric Vehicle
249
Hardware in the Loop Simulation of a FPGA-based Speed and Position Observer for non-Salient Permanent Magnet Synchronous Motors
250
Hardware in the loop simulation of A.C. drive with the induction motor
251
Hardware in the loop simulation of arbitrary magnitude shaped correlated radar clutter
252
Hardware in the loop simulation of DG integration to the distribution grid using RTDS and dSPACE
253
Hardware in the loop simulation of direct synthesis based two degree of freedom PID control of DC-DC boost converter using Real Time Digital Simulation in FPGA
254
Hardware in the loop simulation of embedded automotive control system
255
Hardware in the loop simulation of non linear control methods applied for power converters
256
Hardware in the loop simulation of railway traffic re-scheduling by means of MILP algorithm
257
Hardware in the loop simulation of robot manipulators through Internet in mechatronics education
258
Hardware in the loop simulation of vehicle controller unit for fuel cell/battery hybrid bus
259
Hardware in the Loop Test for Power System Modeling and Simulation
260
Hardware in the Loop Test for Relay Model Validation
261
Hardware in the loop test of avionics systems
262
Hardware in the loop testing of a steam turbine bypass regulator using a TI C2000 micro-controller
263
Hardware in the loop test-rig for pantograph active control evaluation
264
Hardware in the loop tests for upper stage control systems of Korean space launch vehicle
265
Hardware in the loop wind turbine emulator
266
Hardware independent optical logic operations
267
Hardware Index to Permutation Converter
268
Hardware influence in the stability of recurrent neural networks
269
Hardware integrated quantization solution for improvement of computational H.264 encoder module
270
Hardware integration for an integrated modular motor drive including distributed control
271
Hardware interface configuration for motion control of the PUMA-560 and the Mitsubishi RM-501 robots
272
Hardware interface design for real time embedded systems
273
Hardware interface for a 3-DOF surgical robot arm
274
Hardware interface for haptic feedback in laparoscopic surgery simulators
275
Hardware Interfaces for VR Applications: Evaluation on Prototypes
276
Hardware in-the-loop simulation for ABS using 32-bit embedded system
277
Hardware in-the-loop simulation for visual servoing of fixed wing UAV
278
Hardware in-the-loop simulation system based on NI-PXI for operation and control of microgrid
279
Hardware in-the-loop simulation-a rapid prototyping approach for designing mechatronics systems
280
Hardware intrinsic security based on SRAM PUFs: Tales from the industry
281
Hardware invariant protocol disruptive interference
282
Hardware invariant protocol disruptive interference for 100BaseTX Ethernet communications
283
Hardware IP Protection During Evaluation Using Embedded Sequential Trojan
284
Hardware IP Protection through Gate-Level Obfuscation
285
Hardware isolation technique for IRC-based botnets detection
286
Hardware issues migrating legacy TPS to a new tester
287
Hardware Join Java: a high level language for reconfigurable hardware development
288
Hardware join Java: a unified hardware/software language for dynamic partial runtime reconfigurable computing applications
289
Hardware JPEG Decoder and Efficient Post-Processing Functions for Embedded Application
290
Hardware key for information systems users authentification
291
Hardware killed the software star
292
Hardware lab at home possible with ultra low cost boards [logic design course]
293
Hardware laboratories for power electronics and motor drives distance learning courses
294
Hardware Layer Trusted Channel Model Based on the Trusted Platform Control Module
295
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
296
Hardware Limitations of Receiver Channel-Pair Cancellation Ratio
297
Hardware loads and power consumption in cloud computing environments
298
Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor
299
Hardware logger includes advanced facilities
300
Hardware logic simulation by compilation
301
Hardware Loop and Loop Skip Generation Algorithm for the Star Core?? Architecture: Architecture, Application and Compiler Design Interaction in the Embedded Domain
302
Hardware Managers with File System Support for Faster Dynamic Partial Reconfiguration
303
Hardware mass object analyser implementation for stereo camera
304
Hardware metering
305
Hardware method for context searching in intelligent secondary memory
306
Hardware method of synchronising processes without using a clock
307
Hardware methods for detecting global maximum power point in a PV power plant
308
Hardware Microkernels for Heterogeneous Manycore Systems
309
Hardware microprocessor thermal emulation using synthetic heat sources and temperature sensors in FPGA
310
Hardware Minimization of Videotex or Teletext Decoders By Exploitation of Display Redundancy
311
Hardware model checking: Status, challenges, and opportunities
312
Hardware model of a Dynamic Power Flow Controller
313
Hardware model of automatically adaptive cloud computing architecture in 2D matrix grid
314
Hardware model of commonsense reasoning based on Fuzzy Default Logic
315
Hardware modeling and implementation of modified SPIHT algorithm for compression of images
316
Hardware modeling and verification of an ATM ring MAC protocol
317
Hardware modelling of frequency recovery in an upstream demodulator for DOCSIS 3.0
318
Hardware modelling of JPEG2000 MQ-encoder
319
Hardware models for automated partitioning and mapping in multi-core systems
320
Hardware modifications in radix-2 cascade FFT processors
321
Hardware Module Design for Ensuring Trust
322
Hardware module design of a real-time multi-sensor fire detection and notification system using fuzzy logic
323
Hardware module for an adaptive modeling unit of multi-symbol multiplication-free arithmetic encoder
324
Hardware module reuse and runtime assembly for dynamic management of reconfigurable resources
325
Hardware module selection for real time pipeline architectures using probabilistic cost estimation
326
Hardware monitoring of a multiprocessor system
327
Hardware Monitoring of Real-Time Computer System Performance
328
Hardware MPI-2 Functions for Multi-Processing Reconfigurable System on Chip
329
Hardware Multi-processor Design for Highly-Demanding Applications
330
Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems
331
Hardware nested looping of parameterized and embedded DSP core
332
Hardware neural network accelerators
333
Hardware neural network implementation of tracking system
334
Hardware Neuro-Fuzzy Learning
335
Hardware neuron models with CMOS for auditory neural networks
336
Hardware noise generator
337
Hardware nonlinearities in digital TV broadcasting using OFDM modulation
338
Hardware obfuscation using PUF-based logic
339
Hardware Objects for Java
340
Hardware objects of the circuits for robotics
341
Hardware Observability Framework for Minimally Intrusive Online Monitoring of Embedded Systems
342
Hardware of structured brain computer
343
Hardware Operator for Simultaneous Sine and Cosine Evaluation
344
Hardware operators for function evaluation using sparse-coefficient polynomials
345
Hardware optimization for a reconfigurable Polyphase-FFT design using common sub-expression elimination
346
Hardware optimization of complex multiplication scheme for DSP application
347
Hardware optimization of Generalized Pairwise Complementary sequences generation
348
Hardware Optimization Of Underwater Acoustic Models For IBM-compatible PCs
349
Hardware Optimizations for Anytime Perception and Control
350
Hardware optimizations of hard-decision ECC decoders for MLC NAND flash memories
351
Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt
352
Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity
353
Hardware oriented algorithm analysis and modification for high definition AVS video encoder VLSI implementation Digest of technical papers
354
Hardware oriented architectures for continuous-speech speaker-independent ASR systems
355
Hardware oriented category pre-determination algorithm for SAO in HEVC
356
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
357
Hardware oriented fuzzy neural network
358
Hardware oriented optimization of Smith-Waterman algorithm
359
Hardware oriented rate control algorithm and implementation for realtime video coding
360
Hardware oriented rate control algorithm and implementation for realtime video coding
361
Hardware oriented re-design and matrix approximation analysis for transform in High Efficiency Video Coding (HEVC)
362
Hardware oriented semistate descriptions of functional artificial neural networks
363
Hardware OS Communication Service and Dynamic Memory Management for RSoCs
364
Hardware Overhead Reduction for Memory BIST
365
Hardware overview of the EUROGAM data acquisition system
366
Hardware overview of the EUROGAM data acquisition system
367
Hardware paradigm shifts in the optical communication infrastructure with three “M technologies”
368
Hardware Particle Swarm Optimization Based on the Attractive-Repulsive Scheme for Embedded Applications
369
Hardware Particle Swarm Optimization with passive congregation for embedded applications
370
Hardware Partitioning for Big Data Analytics
371
Hardware partitioning software for dynamically reconfigurable SoC design
372
Hardware PCA for gas identification systems using high level synthesis on the Zynq SoC
373
Hardware performance analysis of a parametric CORDIC IP
374
Hardware performance analysis of the SHACAL-2 encryption algorithm
375
Hardware performance and experimental results of portable digital SNG equipment using a flat antenna
376
Hardware performance counter-based problem diagnosis for e-commerce systems
377
Hardware performance estimation by dynamic scheduling
378
Hardware performance of L-band SAR system onboard ALOS-2
379
Hardware performance sniffers for embedded systems profiling
380
Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture
381
Hardware phenomenological effects on cochannel full-duplex MIMO relay performance
382
Hardware pipelining of runtime-detected loops
383
Hardware platform and implementation of a real-time multi-user MIMO-OFDM testbed
384
Hardware Platform Design for Network Performance Closed-Loop Testing System of Smart Substations
385
Hardware platform design for real-time video applications
386
Hardware platform design of dual mode portable navigator based on OMAP-L138
387
Hardware platform for automotive camera based on Ethernet AVB
388
Hardware platform for software enabled radio and smart antennas
389
Hardware platform for software-defined WCDMA/OFDM baseband receiver implementation
390
Hardware platform for testing battery energy storage systems in the presence of renewables
391
Hardware platform for testing performance of TRNGs embedded in actel fusion FPGA
392
Hardware platform for wireless geophysical monitoring
393
Hardware platform to tests the availability of rooms in a medical center
394
Hardware platforms for teaching C, to engineering technology students
395
Hardware Precomputation of Entropy for Anomaly Detection
396
Hardware Prediction for Data Coherency of Scientific Codes on DSM
397
Hardware prediction of OS run-length for fine-grained resource customization
398
Hardware Prefetchers Leak: A Revisit of SVF for Cache-Timing Attacks
399
Hardware prefetching in bus-based multiprocessors: pattern characterization and cost-effective hardware
400
Hardware prefetching techniques for cache memories in multimedia applications
401
Hardware preprocessing for the H1-Level 2 neural network trigger upgrade
402
Hardware primitives for packet flow processing architectures
403
Hardware primitives for the synthesis of multithreaded elastic systems
404
Hardware property checker for run-time Hardware Trojan detection
405
Hardware protection and authentication through netlist level obfuscation
406
Hardware prototype and real-time validation of the satellite communication based Loss-of-Mains protection
407
Hardware Prototype for Two-Way Multi-Hop Relay Network with MIMO Network Coding
408
Hardware prototype to emulate the dynamics of power system generators with field programmable analog arrays
409
Hardware prototyping for the H.264 4×4 transformation [video coding]
410
Hardware prototyping of an intelligent current dq PI controller for FOC PMSM drive
411
Hardware prototyping of boolean function classification schemes for lossless data compression
412
Hardware Prototyping of Network Coding in HDL
413
Hardware prototyping of novel invasive multicore architectures
414
Hardware prototyping through programmable gate arrays
415
Hardware provisions for extended precision floating-point arithmetic
416
Hardware PSO for sensor network applications
417
Hardware pulse mode neural network with piecewise linear activation function neurons
418
Hardware quality audits: a better approach
419
Hardware quality control in the TROPICO system
420
Hardware R&D of the KEK/JAERI 50 GeV synchrotron fast extraction kicker magnets
421
Hardware radial basis functions neural networks for phoneme recognition
422
Hardware real time simulator of Synchronous Reluctance Motor including three phase pwm inverter model
423
Hardware realisable models of neural processing
424
Hardware realisable models of neural processing
425
Hardware realisation of a neuron transfer function and its derivative
426
Hardware realisation of artificial neural network with application to information coding
427
Hardware realisation of binary search algorithm
428
Hardware realizable lattice-reduction-aided detectors for large-scale MIMO systems
429
Hardware realization and optimized of lifting wavelet transform
430
Hardware realization of a 10KVA hybrid active power filter
431
Hardware realization of a 2D IIR semisystolic filter with application to real-time homomorphic filtering
432
Hardware realization of a bio-inspired POEtic tissue
433
Hardware realization of a Fermat number transform
434
Hardware realization of a Hamming neural network with on-chip learning
435
Hardware realization of a Java virtual machine for high performance multimedia applications
436
Hardware realization of a lightweight 2D cellular automata-based cipher for image encryption
437
Hardware realization of a low complexity fading filter for Multipath Rayleigh fading simulator
438
Hardware realization of a medical diagnostic system based on Probabilistic CMOS (PCMOS) technology
439
Hardware realization of a modification to the DQDB protocol to achieve fair network access and full bandwidth utilization
440
Hardware realization of a multistage speech waveform vector quantizater
441
Hardware realization of a novel Automatic Censored Cell Averaging CFAR detection algorithm using FPGA
442
Hardware Realization of an Adaptive Algorithm Using a Microcomputer-Controlled Programmable Analog Filter
443
Hardware realization of an FPGA processor — Operating system call offload and experiences
444
Hardware realization of an XPIC system/measurement method and results
445
Hardware realization of analog CMOS current-mode minimum circuit
446
Hardware realization of autonomous robot localization system
447
Hardware realization of BSB recall function using memristor crossbar arrays
448
Hardware realization of building blocks for artificial neural networks
449
Hardware realization of chaos based block cipher for image encryption
450
Hardware realization of concise evolutionary algorithm on FPEA
451
Hardware realization of DC embedding video watermarking technique based on FPGA
452
Hardware realization of digital signal processing elements using the residue number system.
453
Hardware realization of direct subband transformer with minimum used resources
454
Hardware realization of discrete convolution using CORDIC and Vedic multiplier
455
Hardware realization of discrete event system diagnosers
456
Hardware realization of fast defuzzification by adaptive integration
457
Hardware realization of fast image encoder with minimum memory size
458
Hardware realization of fuzzy adaptive filters for non linear channel equalization
459
Hardware realization of GALS based cortical column systems
460
Hardware realization of heart electrostimulator
461
Hardware realization of high speed elliptic curve point multiplication using multiple Point Doublers and point adders
462
Hardware realization of higher-order CMAC model for color calibration
463
Hardware realization of inverse kinematics for robot manipulators
464
Hardware realization of inverse subband transformer with minimum used resources
465
Hardware realization of Krawtchouk transform using VHDL modeling and FPGAs
466
Hardware realization of Krawtchouk transform utilizing VNDL modeling
467
Hardware realization of locally normalized cross correlation algorithm
468
Hardware realization of Mersenne number transforms for fast digital convolution
469
Hardware Realization of Modified CIC Filter for Satellite Communication
470
Hardware realization of multi-valued exponential bidirectional associative memory using current-mode circuits
471
Hardware realization of novel pulsed neural networks based on delta-sigma modulation with GHA learning rule
472
Hardware realization of panoramic camera with speaker-oriented face extraction for teleconferencing
473
Hardware realization of shadow detection algorithm in FPGA
474
Hardware Realization of Steganographic Techniques
475
Hardware Realization of the AES Algorithm S-Block Functions in the Current-Mode Gate Technology
476
Hardware realization of the Common-ISDN-API message exchange mechanism
477
Hardware realization of the modular exponentiation operation in cryptographic systems based on binary and multivalued logic
478
Hardware Realization Of The MPEG-7 Edge Histogram Descriptor
479
Hardware realization of the reduced cross terms distribution
480
Hardware realization of the system for automated current-voltage characteristics measurement for semiconductor devices
481
Hardware Realization of TLM
482
Hardware realization of UMTS femtocell modem with uplink interference cancellation
483
Hardware realization of Walsh functions and their applications using VHDL and reconfigurable logic
484
Hardware Realization of Waveform Vector Quantizers
485
Hardware reciprocation using degree-3 polynomials but only 1 complete multiplication
486
Hardware reconfigurable wireless sensor network node with power and area efficiency
487
Hardware reconfiguration based on broadcasted digital TV signal
488
Hardware Reconfiguration Capability for Third Generation Sensor Nodes: Design and Challenges
489
Hardware Reconfiguration Capability for Third-Generation Sensor Nodes
490
Hardware reconfiguration scheme for high availability systems
491
Hardware reduction based on M-CSS correlation improvements
492
Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization
493
Hardware reduction for compositional microprogram control unit dedicated for CPLD systems
494
Hardware reduction for FSM - Based control units using PAL technology
495
Hardware reduction for matrix circuit of control Moore automaton
496
Hardware reduction for RAM-based Moore FSMs
497
Hardware reduction in concurrent error detection checkers in linear analog circuits using continuous checksums
498
Hardware Reduction in Digital Delta–Sigma Modulators Via Error Masking—Part II: SQ-DDSM
499
Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input
500
Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input
501
Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM
502
Hardware reduction in digital MASH delta-sigma modulators via error masking
503
Hardware reduction in higher order MASH Digital Delta-Sigma Modulators via error masking
504
Hardware Reduction in Optical Parallel Interference Cancellation
505
Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry
506
Hardware reduction of DSP kernel data path using carry save arithmetic operation in fused add multiply add unit
507
Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture
508
Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processor
509
Hardware reliability
510
Hardware reliability assessment of safety related and safety critical systems in nuclear power plants
511
Hardware reliability of embedded systems: Are we there yet?
512
Hardware Reliability prediction of Computer Based safety Systems of Indian Nuclear Plants
513
Hardware Rendering of 3D Geometry with Elevation Maps
514
Hardware requirements for digital nuclear radiation spectroscopy
515
Hardware Requirements For Functional MRI
516
Hardware requirements for neural network pattern classifiers: a case study and implementation
517
Hardware requirements for neural-net optical character recognition
518
Hardware requirements for optical circuit switched data center networks
519
Hardware Requirements for Secure Computer Systems: A Framework
520
Hardware requirements for the DCS1800 air-interface
521
Hardware requirements of communication-centric machine learning algorithms
522
Hardware requirements to digital VLSI implementation of neural networks
523
Hardware resource allocation for hardware/software partitioning in the LYCOS system
524
Hardware Resource Manager for Reconfiguration System
525
Hardware resource minimization for histogram-based ADC BIST
526
Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems
527
Hardware results demonstrating defect detection using power supply signal measurements
528
Hardware retrofit and computed torque control of a Puma 560 Robot updating an industrial manipulator
529
Hardware reuse at the behavioral level
530
Hardware Reuse Improvement through the Domain Specific Language dHDL
531
Hardware Reuse in Modern Application-Specific Processors and Accelerators
532
Hardware review
533
Hardware rip-up router with concurrent wavefront propagation
534
Hardware rollback recovery schemes for multiprocessor systems
535
Hardware ROV simulation facility for the evaluation of novel underwater manipulation techniques
536
Hardware Runtime Monitoring for Dependable COTS-Based Real-Time Embedded Systems
537
Hardware scale and performance evaluation of a compact subsystem modular optical cross connect that adopts tailored add/drop architecture
538
Hardware scale and performance evaluation of compact OXC add/drop architecture
539
Hardware scale reduction in large-port count OXCs exploiting selective switch based coarse granular routing
540
Hardware Scheduling for dynamic adaptability using external profiling and hardware threading
541
Hardware Scheduling Support in SMP Architectures
542
Hardware schemes for early register release
543
Hardware Scripting in Gel
544
Hardware security device facilitated trusted residential energy services
545
Hardware Security Evaluation Using Assurance Case Models
546
Hardware security for software privacy support
547
Hardware security in practice: Challenges and opportunities
548
Hardware security strategies exploiting nanoelectronic circuits
549
Hardware Security: Preparing Students for the Next Design Frontier
550
Hardware security: Threat models and metrics
551
Hardware selection and clustering in the HYPER synthesis system
552
Hardware Selection and Modeling for a Small Autonomous Surface Vessel
553
Hardware selection for attitude determination and control subsystem of 1U cube satellite
554
Hardware self-tuning and circuit performance monitoring
555
Hardware setup for the next generation of 3D Ultrasound Computer Tomography
556
Hardware sharing in tree-structure QMF banks
557
Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform
558
Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets
559
Hardware Simplification to the Delta Path in a MASH 111 Delta–Sigma Modulator
560
Hardware simulation model suitable for recursive computations: Karatsuba-Ofman´s multiplication algorithm
561
Hardware simulation of yeast glycolytic oscillations
562
Hardware simulation with software modeling for enhanced architecture performance analysis
563
Hardware simulation: a flexible approach to verification and performance evaluation of communication protocols
564
Hardware simulator assists mobile satellite experiment
565
Hardware simulator design for LTE applications with time-varying MIMO channels
566
Hardware simulator development for PMSG wind power system
567
Hardware simulator for dynamic performance analysis of DC microgrid system
568
Hardware Simulator for MIMO Radio Channels: Design and Features of the Digital Block
569
Hardware simulator for PMSG wind power system with matrix converter
570
Hardware simulator: Digital block design for time-varying MIMO channels with TGn model B test
571
Hardware Single-Switch Keyboard and Mouse Replacement for Computer Control
572
Hardware software co-design of a fast bilateral filter in FPGA
573
Hardware software codesign of a safety-critical embedded computer system for an automatic endoscope
574
Hardware software codesign of DSP system using grammar based approach
575
Hardware software co-design of pipelined instruction decoder in system emulation
576
Hardware software co-design of the Aho-Corasick algorithm: Scalable for protein identification?
577
Hardware software co-design using profiling and clustering
578
Hardware software co-simulation of dual image encryption using Latin square image
579
Hardware software partitioning of task graph using genetic algorithm
580
Hardware Software Partitioning Problem in Embedded System Design Using Particle Swarm Optimization Algorithm
581
Hardware software partitioning using genetic algorithm
582
Hardware Software Partitioning Using Immune Algorithm Based on Pareto
583
Hardware Software Partitioning using Particle Swarm Optimization Technique
584
Hardware software partitioning with integrated hardware design space exploration
585
Hardware software system design of a generic embedded controller for industrial applications
586
Hardware software tri-design of encryption for mobile communication units
587
Hardware solution for detection and prevention of buffer overflow attacks
588
Hardware Solution for Real-Time Face Recognition
589
Hardware solution of a polyphase filter bank for MP3 audio processing
590
Hardware solution of chaos based image encryption
591
Hardware solution of real-time depth estimation based on stereo vision
592
Hardware solution to Java compressed heap
593
Hardware Solutions for Biofeedback and Game Interactions
594
Hardware solutions for fuzzy control
595
Hardware specialization of machine-learning kernels: Possibilities for applications and possibilities for the platform design space (Invited)
596
Hardware specification and system performance of Dual-channel Radiometers for Earth and Atmosphere Monitoring (DREAM) flight model
597
Hardware Specification with Temporal Logic: An Example
598
Hardware speech recognition for user interfaces in low cost, low power devices
599
Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot
600
Hardware spiking neurons design: Analog or digital?
601
Hardware starting approximation for the square root operation
602
Hardware starting approximation method and its application to the square root operation
603
Hardware strategies for end-point detection
604
Hardware stream cipher with controllable chaos generator for colour image encryption
605
Hardware Strengthening a Distributed Logging Scheme
606
Hardware structure for Walsh-Hadamard transforms
607
Hardware structure of 2D to 3D image conversion system for digital archives
608
Hardware structure of a new general-purpose radar signal processing system
609
Hardware structures and digital signal processor for image processing on real time
610
Hardware support for a hash-based IP traceback
611
Hardware Support for Accelerating Data Movement in Server Platform
612
Hardware Support for Advanced Data Management Systems
613
Hardware support for arbitrarily complex loop structures in embedded applications
614
Hardware Support for Arithmetic Units of Processor with Multimedia Extension
615
Hardware Support for Automatic Routing
616
Hardware support for backward error recovery
617
Hardware Support for Broadcast and Reduce in MPSoC
618
Hardware support for bulk data movement in server platforms
619
Hardware support for CAN fault-tolerant communication
620
Hardware Support for Combined Interval and Floating Point Multiplication
621
Hardware support for communication networks, ISDN: the I420 interface standard and associated chip support
622
Hardware support for concurrent garbage collection in SMP systems
623
Hardware support for control transfers in code caches
624
Hardware support for controlled interaction of guaranteed and best-effort communication
625
Hardware Support for Cost-Effective System-Level Protection in Multi-core SoCs
626
Hardware support for dynamic scheduling in multiprocessor Operating System
627
Hardware Support for Efficient Data Classification
628
Hardware support for efficient execution of Ada tasking
629
Hardware Support for Efficient Sparse Matrix Vector Multiplication
630
Hardware support for extracting coarse-grain speculative parallelism in distributed shared-memory multiprocessors
631
Hardware Support for Fast Reconfigurability in Progress Arrays
632
Hardware support for fault tolerance in triple redundant CAN controllers
633
Hardware support for flexible distributed shared memory
634
Hardware support for floating point map function generation
635
Hardware support for high performance, intrusion- and fault-tolerant systems
636
Hardware support for interprocess communication
637
Hardware Support For Large Atomic Units in Dynamically Scheduled Machines
638
Hardware Support for MPI in DIMMnet-2 Network Interface
639
Hardware support for performance measurements and energy estimation of OpenRISC processor
640
Hardware Support for Prescient Instruction Prefetch
641
Hardware support for priority inheritance
642
Hardware support for production run diagnosis of performance bugs
643
Hardware support for QoS-based function allocation in reconfigurable systems
644
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
645
Hardware support for real-time operating systems
646
Hardware Support for Relaxed Concurrency Control in Transactional Memory
647
Hardware support for release consistency with queue-based synchronization
648
Hardware support for resource partitioning in real-time embedded systems
649
Hardware support for RSVP capable routing
650
Hardware Support for Safe Execution of Native Client Applications
651
Hardware Support for Safety Interlocks and Introspection
652
Hardware Support for Safety-Critical Java Scope Checks
653
Hardware Support for Secure Processing in Embedded Systems
654
Hardware Support for Secure Processing in Embedded Systems
655
Hardware support for synchronization in the Scalable Coherent Interface (SCI)
656
Hardware support for the Seamless programming model
657
Hardware support of JPEG
658
Hardware support to operations of relational algebra
659
Hardware Support Vector Machine (SVM) for satellite on-board applications
660
Hardware support: a cache lock mechanism without retry
661
Hardware Supported Adaptive Data Collection for Networks on Chip
662
Hardware Supported Multicast in 2-D Mesh InfiniBand Networks
663
Hardware Supported Task Scheduling on Dynamically Reconfigurable SoC Architectures
664
Hardware supported technique for detecting multi-corners in digital contours
665
Hardware Supported Time Synchronization in Multi-core Architectures
666
Hardware Supporting Project to Prolong the Lifetime of the Wireless Sensor Networks
667
Hardware supports for efficient barrier synchronization on 2-D mesh networks
668
Hardware synchronization for embedded multi-core processors
669
Hardware synchronization of massively parallel processes in distributed systems
670
Hardware Synthesis for Asynchronous Communications Mechanisms
671
Hardware synthesis for multi-dimensional time
672
Hardware synthesis for neural networks from a behavioral description with VHDL
673
Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators
674
Hardware synthesis for stack type partitioned-bus architecture
675
Hardware synthesis from a recursive functional language
676
Hardware synthesis from C/C++
677
Hardware synthesis from C/C++ models
678
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
679
Hardware synthesis from DDL
680
Hardware synthesis from encapsulated Verilog modules
681
Hardware synthesis from guarded atomic actions with performance specifications
682
Hardware synthesis from requirement specifications
683
Hardware Synthesis from Software-Oriented UML Descriptions
684
Hardware synthesis from SPDF representation for multimedia applications
685
Hardware synthesis of an ATM multiplexer from SDL to VHDL: a case study
686
Hardware synthesis of artificial neural networks using field programmable gate arrays and fixed-point numbers
687
Hardware Synthesis of Explicit Model Predictive Controllers
688
Hardware synthesis of recursive functions through partial stream rewriting
689
Hardware synthesis with the Bach system
690
Hardware system design of radionuclide monitoring in seawater
691
Hardware system design of SD card reader and image processor on FPGA
692
Hardware system for biologically realistic, plastic, and real-time spiking neural network simulations
693
Hardware system synthesis from Domain-Specific Languages
694
Hardware task migration module for improved fault tolerance and predictability
695
Hardware task scheduling for heterogeneous soc architectures
696
Hardware task scheduling optimizations for reconfigurable computing
697
Hardware Task/Processor Scheduling in a Polyprocessor Environment
698
Hardware Task-Status Manager for an RTOS with FIFO communication
699
Hardware techniques
700
Hardware techniques for testing software components
701
Hardware Technologies for High-Performance Data-Intensive Computing
702
Hardware Technologies For Pen-based Computers
703
Hardware technology and architecture of the NEC SX-3/SX-X supercomputer system
704
Hardware technology for Hitachi M-880 processor group
705
Hardware technology for the Hitachi MP5800 series (HDS Skyline Series)
706
Hardware Technology in the Year 2001
707
Hardware Test Technology
708
Hardware testing for error tolerant multimedia compression based on linear transforms
709
Hardware that produces bounded rather than exact results
710
Hardware then and now
711
Hardware thread-context switching
712
Hardware Thread-Level Speculation Performance Analysis
713
Hardware Threat: The Challenge of Information Security
714
Hardware timebase calibration in the multi-GSa/s LABRADOR-4 ASIC
715
Hardware timestamping for image acquisition system based on FlexRIO and IEEE 1588 v2 standard
716
Hardware timing verification using KRONOS
717
Hardware to compute Walsh coefficients
718
Hardware to software migration with real-time thread integration
719
Hardware to support runtime intelligence
720
Hardware toolkit for studying chaos: a live demonstration of nonlinear dynamics instrumentation with audience participation
721
Hardware Topics of an MF-AM Traffic Information Broadcasting Service
722
Hardware Tracking Related to Compact Medical Pulse Synchrotron
723
Hardware Transactional Memory in Multicore Processors
724
Hardware transactional memory on multi-processor FPGA platform
725
Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps
726
Hardware Transactional Memory Supporting I/O Operations within Transactions
727
Hardware transactional memory system for parallel programming
728
Hardware Transactional Memory with Delayed-Committing
729
Hardware Trojan Attacks: Threat Analysis and Countermeasures
730
Hardware Trojan detection acceleration based on word-level statistical properties management
731
Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis
732
Hardware Trojan detection by delay and electromagnetic measurements
733
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis
734
Hardware Trojan detection by specifying malicious circuit properties
735
Hardware trojan detection by symmetry breaking in path delays
736
Hardware Trojan detection for gate-level ICs using signal correlation based clustering
737
Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline
738
Hardware Trojan detection methodology for FPGA
739
Hardware Trojan detection through golden chip-free statistical side-channel fingerprinting
740
Hardware Trojan detection using exhaustive testing of k-bit subspaces
741
Hardware Trojan detection using path delay fingerprint
742
Hardware Trojan detection via current measurement: A method immune to process variation effects
743
Hardware Trojan detection with linear regression based gate-level characterization
744
Hardware Trojan for security LSI
745
Hardware Trojan for ultra lightweight block cipher Piccolo
746
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry
747
Hardware Trojan horse detection using gate-level characterization
748
Hardware Trojan Horse Device Based on Unintended USB Channels
749
Hardware Trojan Horses in Cryptographic IP Cores
750
Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream
751
Hardware Trojan prevention based on Fully Homomorphic Encryption
752
Hardware Trojan prevention using layout-level design approach
753
Hardware Trojan Protection for Third Party IPs
754
Hardware Trojan self-detector
755
Hardware trojan state detection for analog circuits and systems
756
Hardware Trojan: Threats and emerging solutions
757
Hardware Trojans embedded in the dynamic operation of analog and mixed-signal circuits
758
Hardware Trojans hidden in RTL don´t cares ? Automated insertion and prevention methodologies
759
Hardware Trojans in asynchronous FIFO-buffers: From clock domain crossing perspective
760
Hardware Trojans in Wireless Cryptographic ICs
761
Hardware Trojans in wireless cryptographic ICs: Silicon demonstration & detection method evaluation
762
Hardware Trojans: current challenges and approaches
763
Hardware Trojans: The defense and attack of integrated circuits
764
Hardware unit for OVSF/Walsh/Hadamard code generation [3G mobile communication applications]
765
Hardware Upgrade for Klystrons in the SLC
766
Hardware validated TCAD simulation of polysilicon resistor including trap physics and self-heating
767
Hardware Variability-Aware Duty Cycling for Embedded Sensors
768
Hardware Verification
769
Hardware Verification
770
Hardware verification of a hyper-efficient (98%) and super-compact (2.2kW/dm3) isolated AC/DC telecom power supply module based on multi-cell converter approach
771
Hardware verification using ANSI-C programs as a reference
772
Hardware Verification Using Software Analyzers
773
Hardware verification using symbolic state transition graphs
774
Hardware verification, Boolean logic programming, Boolean functional programming
775
Hardware verification: ternary algebra versus a hybrid method
776
Hardware version for two-dimensional cellular automata
777
Hardware versus hybrid data prefetching in multimedia processors: a case study
778
Hardware versus software implementation of COMA
779
Hardware virtual components compliant with communication system standards
780
Hardware virtualization based security solution for embedded systems
781
Hardware virtualization for rapid and secure CE product development and life cycle management
782
Hardware Virtualization on Coarse-Grained Reconfigurable Architectures
783
Hardware virtualization support for shared resources in mixed-criticality multicore systems
784
Hardware virtualized flexible network for wireless data-center optical interconnects [invited]
785
Hardware vs software: The two faces of computers
786
Hardware vs. software design tradeoffs for maintenance functions in high-reliability real time systems
787
Hardwareߝsoftware tradeoffs in testing
788
Hardware–Software Codesign of Automatic Speech Recognition System for Embedded Real-Time Applications
789
Hardware–Software Coherence Protocol for the Coexistence of Caches and Local Memories
790
Hardware, Design and Implementation Issues on a Fpga-Based Smart Camera
791
Hardware, Firmware and Software Architecture of the DAQ for High-Resolution Position-Sensing Silicon Drift Detectors With Multiple-Pulse Processing Capability
792
Hardware, software and algorithmic solutions for quantum data processing
793
Hardware, software and mechanical cosimulation for automotive applications
794
Hardware/compiler codevelopment for an embedded media processor
795
Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard
796
Hardware/Firmware Considerations for Integrating Load Management into System Operations
797
Hardware/Firmware Considerations for Integrating Load Management into System Operations
798
Hardware/Firmware Verification of Graphic IP
799
Hardware/Firmware/Software Engineers [advertisement]
800
Hardware/hybrid transactional memory
801
Hardware/software approach for code synchronization in low-power multi-core sensor nodes
802
Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers
803
Hardware/software approache for the FPGA implementation of a fuzzy logic controller
804
Hardware/software architecture for flash memory storage systems
805
Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments
806
Hardware/Software Based Hierarchical Self Test for SoCs
807
Hardware/software co-compilation with the Nymble system
808
Hardware/software co-configuration for multiprocessor SoPC (work-in-progress report)
809
Hardware/software co-debugging for reconfigurable computing
810
Hardware/software co-design
811
Hardware/software co-design
812
Hardware/software codesign and rapid prototyping of embedded systems
813
Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard
814
Hardware/software co-design approach for a DCT-based watermarking algorithm
815
Hardware/software co-design architecture for Blokus Duo solver
816
Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms
817
Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors
818
Hardware/software co-design architecture for thermal management of chip multiprocessors
819
Hardware/software co-design flavors of elliptic curve scalar multiplication
820
Hardware/Software Codesign for a Fuzzy Autonomous Road-Following System
821
Hardware/software co-design for a wireless sensor network platform
822
Hardware/software co-design for accelerating human action recognition
823
Hardware/Software Codesign for an Iris Biometric Search Engine
824
Hardware/software co-design for data-driven Xputer-based accelerators
825
Hardware/software codesign for digital communication processing
826
Hardware/software codesign for DSP (from the Guest Editor)
827
Hardware/software co-design for DSP applications via the HMS framework
828
Hardware/software codesign for embedded signal processing
829
Hardware/software co-design for energy-efficient seismic modeling
830
Hardware/software co-design for fast-trainable speaker identification system based on SMO
831
Hardware/software codesign for FPGA-based systems
832
Hardware/software co-design for high performance computing: Challenges and opportunities
833
Hardware/software co-design for IP objects based on CORBA
834
Hardware/software co-design for line detection algorithm on FPGA
835
Hardware/Software Co-Design for Matrix Computations on Reconfigurable Computing Systems
836
Hardware/software Co-design for near real time enhancement of remote sensing imaging
837
Hardware/software co-design for particle swarm optimization algorithm
838
Hardware/software co-design for real-time physical modeling
839
Hardware/software codesign for signal processing systems. A survey and new results
840
Hardware/software codesign for video compression using the EXECUBE processing array
841
Hardware/software co-design for virtual machines
842
Hardware/Software codesign for watermarking in DCT domain
843
Hardware/Software Codesign Guidelines for System on Chip FPGA-Based Sensorless AC Drive Applications
844
Hardware/Software Co-design Implementation of On-Chip Backpropagation
845
Hardware/software co-design in extensible processing platforms for combinatorial search algorithms
846
Hardware/software co-design in the rapid prototyping of application-specific signal processors methodology
847
Hardware/software co-design in USB 3.0 mass storage application
848
Hardware/software co-design language compatible with VHDL
849
Hardware/software codesign methodology for fuzzy controller implementation
850
Hardware/software co-design of a dynamically configurable SHA-3 System-on-Chip (SoC)
851
Hardware/software co-design of a fingerprint recognition system
852
Hardware/software co-design of a fuzzy RISC processor
853
Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics
854
Hardware/software co-design of a high-end mixed signal microcontroller
855
Hardware/software co-design of a Java virtual machine
856
Hardware/Software co-design of a key point detector on FPGA
857
Hardware/Software Codesign of a Low-Cost Rate Control Scheme for H.264/AVC
858
Hardware/software codesign of a scalable embedded radar signal processor
859
Hardware/Software Co-design of a Secure Ubiquitous System
860
Hardware/software co-design of a SIMD-DSP-based DVB-T receiver
861
Hardware/Software Codesign of Aerospace and Automotive Systems
862
Hardware/Software Co-design of an ADALINE Based Adaptive Controller for a DC Motor
863
Hardware/software co-design of an ATCA-based computation platform for data acquisition and triggering
864
Hardware/software co-design of an ATM network interface card: a case study
865
Hardware/software co-design of an avionics communication protocol interface system: an industrial case study
866
Hardware/software codesign of an avionics protocol interface system
867
Hardware/software co-design of an elliptic curve public-key cryptosystem
868
Hardware/Software Co-Design of an FPGA-based Embedded Tracking System
869
Hardware/software co-design of communication protocols
870
Hardware/Software Co-design of Control Algorithms
871
Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms
872
Hardware/software co-design of digital telecommunication systems
873
Hardware/software co-design of Dynamic Binary Translation in X86 emulation
874
Hardware/software co-design of elliptic curves public-key cryptosystems
875
Hardware/software co-design of elliptic-curve cryptography for resource-constrained applications
876
Hardware/software co-design of embedded image processing system using systemc modeling platform
877
Hardware/software codesign of embedded systems the SPI workbench
878
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs
879
Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems
880
Hardware/software Co-design of NLMS adaptive filters on FPGA
881
Hardware/software co-design of particle filter and its application in object tracking
882
Hardware/software co-design of power level difference based noise cancellation
883
Hardware/Software Codesign of Resource Constrained Real-Time Systems
884
Hardware/Software Co-Design of RTOS-Based Platforms
885
Hardware/software codesign of TDMA MAC applied to IEEE 802.16 subscriber station
886
Hardware/software co-design of the Stanford FLASH multiprocessor
887
Hardware/software co-design of video processing applications on a reconfigurable platform
888
Hardware/Software Codesign Pedagogy for the Industry
889
Hardware/Software Codesign to Optimize SoC Device Battery Life
890
Hardware/software co-design to secure crypto-chip from side channel analysis at design time
891
Hardware/Software co-design using artificial neural network and evolutionaryy computing
892
Hardware/software co-design using hierarchical platform-based design method
893
Hardware/software co-design using high level synthesis for cryptographic module
894
Hardware/software codesign: a perspective
895
Hardware/software codesign: a systematic approach targeting data-intensive applications
896
Hardware/Software Codesign: The Past, the Present, and Predicting the Future
897
Hardware/software co-designed accelerator for vector graphics applications
898
Hardware/Software Coevolution of Genome Programs and Cellular Processors
899
Hardware/Software Communication Middleware for Data Adaptable Embedded Systems
900
Hardware/software co-modeling of SAT solver based on distributed computing elements using SystemC
901
Hardware/Software Convergence for C4ISR/EW
902
Hardware/software co-reliability of configurable digital systems
903
Hardware/Software Co-Simulation
904
Hardware/software co-simulation environment for CSoC with soft processors
905
Hardware/Software Co-Simulation for Last Level Cache Exploration
906
Hardware/software co-simulation for the rapid prototyping of an acceleration sensor system with force-feedback control
907
Hardware/software cosimulation from interface perspective
908
Hardware/software Co-simulation In A Vhdl-based Test Bench Approach
909
Hardware/software co-simulation methodology based on two alternative approaches
910
Hardware/software co-simulator for ASIC DSP chips
911
Hardware/software cost analysis of interrupt processing strategies
912
Hardware/software co-synthesis with memory hierarchies
913
Hardware/software co-synthesis with memory hierarchies
914
Hardware/software cosynthesis: multiple constraint satisfaction and component retrieval
915
Hardware/software co-testing of embedded memories in complex SOCs
916
Hardware/software co-training by FPGA/ASIC synthesis and programming of a RISC microprocessor-core
917
Hardware/software co-training lab: from VHDL bit-level coding up to CASE-Tool based system modeling
918
Hardware/software covalidation
919
Hardware/software co-verification of cryptographic algorithms using Cryptol
920
Hardware/Software co-verification platform for EOS design
921
Hardware/software co-verification scheme for MSTP ASIC
922
Hardware/software co-verification, an IP vendors viewpoint
923
Hardware/software debugging of large scale many-core architectures
924
Hardware/Software Design Considerations for Automotive Embedded Systems
925
Hardware/Software Design of Digital Systems
926
Hardware/software design space exploration for a reconfigurable processor
927
Hardware/Software development of a System on Chip platform for VoIP application
928
Hardware/Software Exploration for an Anti-collision Radar System
929
Hardware/software fault tolerance with multiple task modular redundancy
930
Hardware/software formal co-verification using hardware verification techniques
931
Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications
932
Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores
933
Hardware/software implementation of a discrete cosine transform algorithm using SystemC
934
Hardware/software implementation of an on-line machine learning algorithm
935
Hardware/software implementation of PI/PD-like fuzzy controller for high performance motor drives
936
Hardware/software implementation of the EEG signal compression module for an ambulatory monitoring subsystem
937
Hardware/software infrastructure for ASIC commissioning and rapid system prototyping
938
Hardware/software instruction set configurability for system-on-chip processors
939
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths
940
Hardware/software integration in solar polarimetry
941
Hardware/software interface codesign for embedded systems
942
Hardware/software interface for high-performance space computing with FPGA coprocessors
943
Hardware/software interface for multi-dimensional processor arrays
944
Hardware/software IP protection
945
Hardware/software managed scratchpad memory for embedded system
946
Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks
947
Hardware/Software Method of Digital SoC Verification
948
Hardware/software optimization of error detection implementation for real-time embedded systems
949
Hardware/software organization of a high-performance ATM host interface
950
Hardware/software package for CTD data acquisition with a Neil Brown CTD
951
Hardware/Software Partitioned Implementation of Real-time Object-oriented Camera for Arbitrary-shaped MPEG-4 Contents
952
Hardware/Software partitioning algorithm based on wavelet mutation binary particle swarm optimization
953
Hardware/Software partitioning algorithm for embedded systems with repeated functionalities
954
Hardware/software Partitioning And Pipelining
955
Hardware/Software Partitioning and Scheduling Algorithm Based on FPGA
956
Hardware/Software Partitioning and Static Task Scheduling on Runtime Reconfigurable FPGAs using a SMT Solver
957
Hardware/Software Partitioning for Heterogeneous Multicore SoC Using Genetic Algorithm
958
Hardware/Software partitioning for heterogeneous multicore SOC using particle swarm optimization and immune clone (PSO-IC ) algorithm
959
Hardware/software partitioning for multifunction systems
960
Hardware/software partitioning for multi-function systems
961
Hardware/software partitioning for performance enhancement
962
Hardware/software partitioning for platform-based design method
963
Hardware/software partitioning for telecommunications systems
964
Hardware/Software Partitioning in Embedded System Based on Novel United Evolutionary Algorithm Scheme
965
Hardware/Software Partitioning of a Bayesian Spam Filter via Hardware Profiling
966
Hardware/software partitioning of embedded system in OCAPI-xl
967
Hardware/software partitioning of embedded System-on-Chip applications
968
Hardware/software partitioning of embedded systems with multiple hardware processes
969
Hardware/software partitioning of multirate system using static scheduling theory
970
Hardware/software partitioning of operating systems [SoC applications]
971
Hardware/software partitioning of operating systems: focus on deadlock detection and avoidance
972
Hardware/software partitioning of real-time systems
973
Hardware/software partitioning of software binaries
974
Hardware/software partitioning of software binaries: a case study of H.264 decode
975
Hardware/software partitioning of VHDL system specifications
976
Hardware/Software Partitioning Using Bayesian Belief Networks
977
Hardware/software partitioning using integer programming
978
Hardware/software partitioning with iterative improvement heuristics
979
Hardware/Software Process Migration and RTL Simulation
980
Hardware/software prototyping of dependable real-time system for elderly health monitoring
981
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
982
Hardware/software selected cycle solution
983
Hardware/software solution for high precision defect correction in digital image sensors
984
Hardware/software solution for the automation and real-time control of a wine bottling production line
985
Hardware/software specialization through aspects: The LARA approach
986
Hardware/software strategies in DC brushless motor development
987
Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL
988
Hardware/software system for characterization of microwave electronics materials
989
Hardware/software techniques for DRAM thermal management
990
Hardware/software trade-offs for advanced 3G channel coding
991
Hardware/Software trade-offs: Hardware Design Viewpoint
992
Hardware/Software Vectorization for Closeness Centrality on Multi-/Many-Core Architectures
993
Hardware/software-based diagnosis of load-store queues using expandable activity logs
994
Hardware/software-cosimulation for mechatronic system design
995
Hardware-accelerated 3D visualization of mass spectrometry data
996
Hardware-accelerated adaptive EWA volume splatting
997
Hardware-accelerated address-event processing for high-speed visual object recognition
998
Hardware-accelerated attribute mapping for interactive visualization of complex 3D trajectories
999
Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing
1000
Hardware-accelerated edge detection for polarimetric synthetic aperture radar data
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