<< مقالات لاتين فني مهندسي >>
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1
AMSR/AMSR-E sea surface temperature algorithm development
2
AMSR2 soil moisture downscaling using multisensor products through machine learning approach
3
AMSR2 validation results
4
AMSR-E Accomplishments and Ongoing Activities
5
AMSR-E advanced wind speed retrieval algorithm and its application to marine weather systems
6
AMSR-E and its follow-on, AMSR2
7
AMSR-E Data Resampling With Near-Circular Synthesized Footprint Shape and Noise/Resolution Tradeoff Study
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AMSR-E image classification based on SVM for flood and waterlogging monitoring
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AMSR-E observations of rain and flood events over vegetated areas of LA Plata basin
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AM-SRL: Adaptive Multicast operation of the Supernode-based Reverse Labeling algorithm
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AMSTE precision fire control tracking overview
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Amsterdam 2008, Bridging Gaps
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Amsterdam 2008, bridging gaps
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Amsterdam 2008, bridging gaps
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AMSU Millimeter-Wave Precipitation Retrievals Trained with MM5 Simulations: Sensitivity to Physical Assumptions
16
AMSU-A antenna pattern corrections
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AMsystem: the associative memories readout system
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AMT center set up to ´advance manufacturing´
19
AMT centre set up to ´advance manufacturing´
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AMT eCmoves into CIM
21
AMT failed mode analysis by integration of hardware-in-loop and DFMEA
22
AMT research based on the electric drive system
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AMT starting process analysis and clutch thermal balance estimation model
24
AMT: the story so far
25
AMTA 2004 final call for papers
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AMTA 2005 - 1st Call for Papers
27
AMTA 2006 [AMTA Corner]
28
AMTA 2006 International Program Committee
29
AMTA 2006 International Program Committee
30
AMTA 2008
31
AMTA 2008
32
AMTA 2008 call for papers
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AMTA 2013
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AMTA 2013
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AMTA 2013
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AMTA 2013
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AMTA 2013
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AMTA 2013
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AMTA 2013
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AMTA 2013
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AMTA 2014
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AMTA 2014
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AMTA Asia 2005 technical tour
44
AMTA Coner
45
AMTA Coner [Guest Editor´s Introduction]
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AMTA Corner
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AMTA Corner
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AMTA Corner
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AMTA Corner
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AMTA corner
107
AMTA Corner [October edition]
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AMTA goes Asia! 2005
109
AMTA holds first short course in Asia
110
AMTA Presents: High Level European Antenna Symposium and Exhibition in Munich!
111
AMTA2012
112
AMTEA: Tool for creating and exploiting annotations in the context of Economic Intelligence (competitive intelligence)
113
AMTEC cells challenge energy converters
114
AMTEC electrochemical heat-to electricity conversion defies second law
115
AMTEC flight experiment progress and plans
116
AMTEC powered residential furnace and auxiliary power
117
AMTEC radioisotope power system design and analysis for Pluto Express Fly-By
118
AMTEC recirculating test cell component testing and operation
119
AMTEC: current status and vision
120
AMTES: An Adaptive Tele-education System for Pressure Ulcer Education
121
AMTex 87 preview feature
122
Amtex show was no failure
123
AMTex87 show guide
124
AMTHA: An Algorithm for Automatically Mapping Tasks to Processors in Heterogeneous Multiprocessor Architectures
125
AM-to-PM conversion and intermodulation in nonlinear devices
126
AM-to-PM conversion in varactor-tuned oscillators
127
AM-to-PM Transfer as Reflection of Phase Concavity
128
AMTP: a multipath multimedia streaming protocol for mobile ad hoc networks
129
Amtrak´s high-speed trainset program
130
Amtrak´s next generation passenger locomotive
131
AMTree: an active approach to multicasting in mobile networks
132
AM-Trie: An OC-192 Parallel Multidimensional Packet Classification Algorithm
133
AmTRUE: Authentication Management and Trusted Role-based Authorization in Multi-Application and Multi-User Environment
134
AMUEM 2005 - Proceedings of the 2005 IEEE International Workshop on Advanced Methods for Uncertainty Estimation in Measurement [13 May 2005]
135
AMUEM 2005 Keynote
136
AMUEM 2005 Session A1 - Uncertainty Expression and the GUM
137
AMUEM 2005 Session A2 - Case Studies for Uncertainty Estimation 1
138
AMUEM 2005 Session A3 - Case Studies for Uncertainty Estimation 2
139
AMUEM 2005 Session M1 - Uncertainty Modeling and Expression 1
140
AMUEM 2005 Session M2 - Uncertainty Modeling and Expression 2
141
AMUEM 2005 Table of contents
142
AMUEM 2008 - IEEE workshop on advanced methods for uncertainty estimation measurement proceedings
143
AMul: Adaptive multicast routing protocol for Multi-hop Wireless Networks
144
AMULET: automatic multisensor speech labelling and event tracking: study of the spatio-temporal correlations in voiceless plosive production
145
AMULET1: a micropipelined ARM
146
AMULET1: an asynchronous ARM microprocessor
147
AMULET2e: an asynchronous embedded controller
148
AMULET2e: an asynchronous embedded controller
149
AMULET3 revealed
150
AMULET3: a 100 MIPS asynchronous embedded processor
151
AMULET3: a high-performance self-timed ARM microprocessor
152
AMULET3i cache architecture
153
AMULET3i-an asynchronous system-on-chip
154
AMulti-Agent Collabor ative Fr amework for Mobile E-Health
155
Amulti-channel active fiber-optic feedthrough with stamped mirrors for avionic transceivers
156
Amultidisciplinary model-based test and integration infrastructure
157
Amulti-level phase/frequency detector for clock and data recoveryapplications
158
AMUN - autonomic middleware for ubiquitous environments applied to the smart doorplate project
159
AMUN: an object oriented model for cooperative spatial information systems
160
Amundsen Sea Bathymetry: The Benefits of Using Gravity Data for Bathymetric Prediction
161
AMUSE - A Platform for Prototyping Live Mobile TV Services
162
AMUSE: a minimally-unsatisfiable subformula extractor
163
AMUSE: a new blind identification algorithm
164
AMUSE: advanced broadband services trials for residential users
165
AMUSE: an agent-based middleware for context-aware ubiquitous services
166
AMUSE: Empowering users for cost-aware offloading with throughput-delay tradeoffs
167
Amusing reading
168
Amusing reading-S.Q.J.
169
Amusing Science (review of "The Hysterical Background of Radio") [Book/Software Reviews]
170
AM-video distribution system with 64-way passive optical splitting
171
AMVP prediction algorithm for adaptive parallel improvement of HEVC
172
AMVPayword: Secure and Efficient Anonymous Payword-Based Micropayment Scheme
173
AMVP-Cloud: A Framework of Adaptive Mobile Video Streaming and User Behavior Oriented Video Pre-fetching in the Clouds
174
AMVSC: A framework of adaptive mobile video streaming in the cloud
175
AMVS-NDN: Adaptive mobile video streaming and sharing in wireless named data networking
176
AMW-SMC: A fast and accurate localization method for mobile targets in wireless networks
177
AMY: A simple and secure way to connect devices using pairing-based cryptography
178
AMY: Use your cell phone to create a protected personal network over devices
179
AMYLEX? wire enamel a new cresylic soluble amide-imide
180
Amyloid beta plaque reduction with antibodies crossing the blood brain barrier opened with focused ultrasound in a rabbit model
181
Amyloid Detection Using a Peltier-Based Device [Retrospectroscope]
182
Amyloid fibrils: Dark side of protein aggregation
183
Amyloid-ss Dynamics Correlate with Neurological Status in the Injured Human Brain
184
AMYNA: A security generator framework
185
An "add-on" Analysis of Large irregular Strip Arrays
186
An "Air-core" primary radio frequency permeameter for reversible permeability measurements
187
An "all-p-type" termination structure for silicon microstrip detectors
188
An "almost automatic" and semantic approach for integrating XML sources at various flexibility levels
189
An "Attacker Centric" Cyber Attack Behavior Analysis Technique
190
An "Augmented chain " approach for on-line sensitivity analysis of Markov process
191
AN "E" Field Rod Antenna and Preamplifier for A.M. Field Strength Measurements
192
An "easy axis monitor" for the detailed study of spin transitions.application to ErFeO
3
and Er
3
Fe
5
O
12
193
An "effective" capacitance based delay metric for RC interconnect
194
An "Emo-Statistical" Model for Flexible Dialogue Management
195
An "Energy Star Building" Freshman Engineering Design course
196
An "Equal arc" construction method for positive-negative feedback systems
197
An "Erasure" scheme for atmospheric noise burst interference
198
An "exact" Solution To The Problem Of Calibrating Stokes Matrix Polarimetric Sar Data
199
An "Expert system" for fisheries management
200
An "in the limit" view*
201
An "intent-oriented" approach for Multi-Device User Interface Design
202
An "O" Band Fast PIN Diode Switch
203
An "offshore-resistant" degree program
204
An "ORTHOCORE" magnetic shift register
205
An "SVD+Viterbi" algorithm for multiuser adaptive blind equalization of mobile radio channels
206
An "unrestricted frequency changer" employing force commutated thyristors
207
An "open loop" control methodology for sound reduction inside a car
208
An ω
0
-Q Tunable CMOS Active Inductor for RF Bandpass Filters
209
An Ω(n^2/ log n) Speed-Up of TBR Heuristics for the Gene-Duplication Problem
210
An µTESLA Protocols with Multi-senders Based on a 2-Level XOR Chain with Data-Loss Tolerance
211
An “AC inductor” based grid connected inverter
212
An “energy efficient” vircator-based HPM system
213
An “exponential” slide rule
214
An “inline” quasi-elliptic substrate integrated waveguide filter with high stopband rejection
215
An “Institute of Chemistry”
216
An “load forecasting - dispatching” integration system for multiple boilers in thermal power plants
217
An “M”-shaped beam producing dual stacked reflector antenna for GPS satellite applications
218
An “objects first, tests second” approach for software engineering education
219
An “off-the shelf” synthetic membrane to simplify regeneration of damaged corneas
220
An “on/off” model for energy-efficient scheduling of workflow applications in computational grids
221
An “out of head” sound field enhancement system for headphone
222
An “Umbrella” bound of the Lovász-Gallager type
223
An ℋ
∞
linear parameter-varying (LPV) controller for a diesel engine common rail injection system
224
An ℋ
2
-based direct integral equation solver of linear complexity for full-wave extraction of 3-D structures in multiple dielectrics
225
An ℋ
2
-based linear-complexity solution of surface integral equations for 3-D impedance extraction
226
An ℋ-matrix accelerated direct solver for fast analysis of scattering from structures in layered media
227
An ℋ-matrix parametric cascading based fast direct finite-element solver for large-scale circuit extraction
228
An ℌ
∞
/ℓ
1
approach to cooperative control of multi-agent systems
229
An ℓ
0
−ℓ
1
norm based optimization procedure for the identification of switched nonlinear systems
230
AN ℓ
1/2
regularized low-rank representation for hyperspectral imagery classification
231
An ℓ
1
based post-processing method with an application to ground penetrating radar imaging
232
An ℓ
1
-algorithm for underdetermined systems and applications
233
AN ℓ
1
-TV algorithm for deconvolution with salt and pepper noise
234
An α-β target tracking approach to the benchmark tracking problem
235
An α-approximate algorithm for delay-constraint technology mapping
236
An α-immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell
237
An α-trimmed mean filter controlled by local parameters
238
An ε-approximation approach for global optimization with an application to neural networks
239
An ϵ arithmetic for removing degeneracies
240
An ∞-LQ regulator and sliding mode controller for a flexible structure with synchronous motor
241
An “add-on” analysis of large open circular-cylindrical cavities
242
An “edge-on” silicon strip detector for X-ray imaging
243
An “edge-on” silicon strip detector for X-ray imaging
244
An “NLC-Style” short bunch length compressor in the SLAC linac
245
An “open” DCS solution for cement process control
246
An “unusual” data fusion
247
An ℒ
2
disturbance attenuation approach to the nonlinear benchmark problem
248
An Ω(k
2
) lower bound for area optimization of spiral floorplans
249
An ω-automata approach to the representation of bilevel images
250
An 𝒪(log
2
N)-latency SISO with application to broadband turbo decoding
251
An (
N
-1)-resilient algorithm for distributed termination detection
252
An (8,10) DC-free modulation code
253
An (8158,7136) low-density parity-check encoder
254
An (Al,Ga)As/GaAs heterostructure bipolar transistor with nonalloyed graded-gap ohmic contacts to the base and emitter
255
An (almost) exact solution to general SISO mixed H
2
/H
∞
problems via convex optimization
256
An (architecture-centric) approach for tracing, organizing, and understanding events in event-based software architectures
257
An (ITO or AZO)/ZnO/Cu(In
1−x
Ga
x
)Se
2
superstrate thin film solar cell structure prepared by spray pyrolysis
258
An (n, n) threshold visual cryptography scheme for cheating prevention
259
An (N-1)-resilient algorithm for distributed termination detection
260
An (s,S) inventory control model with return flows
261
An /spl alpha/-immune, 2V supply voltage SRAM using polysilicon PMOS load cell
262
An /spl epsiv/-margin nonlinear classifier based on fuzzy if-then rules
263
An ?1/2-BTV regularization algorithm for super-resolution
264
An ?on scale? simulator for urban DC railway traction application
265
An `add-on´ method for the analysis of scattering from large planar structures
266
An `extended execution time´ software reliability model
267
An `extreme point´ sufficient condition for checking interior instability of interval matrices in the march towards a necessary and sufficient result
268
An `eye-in-hand´ visual inspection system
269
An `introspective´ network that can learn to run its own weight change algorithm
270
An ´add-on´ analysis of large irregular strip arrays
271
An ´add-on´ approach to determining the effect of modification of the geometry of a thin plate on its electromagnetic scattering properties
272
An ´edge´ element solution of electromagnetic transmission through apertures in inhomogeneously loaded cavities
273
An ´electronic tongue´ system based on an array of metallic potentiometric sensors
274
An ´i´ for an ´a´
275
An ´ideal chance´ to access advances
276
An ´in vivo´, in place, regulated battery string ampere hour discharge tester
277
An
E
-field integral equation solution for the radiation from reflector antennas with struts
278
An
H
∞
approach to two degree of freedom design
279
An
H
∞
design procedure using robust stabilization of normalized coprime factors
280
An
H
∞
governor exciter controller design for a power system
281
An
H
∞
-almost disturbance decoupling problem for nonstrictly proper systems-A singular perturbation approach
282
An
H
∞
approach to feedback design with two objective functions
283
An
H
∞
design for aircraft longitudinal flight control
284
An
l
1
-approximation based method for synthesizing FIR filters
285
An
L
-infinity extension of transmission-zero and robust-design notions to global tracking in uncertain nonlinear systems
286
An
M
-matrix and majorant approach to robust stability and performance analysis for systems with structured uncertainty
287
An
M
-matrix and majorant approach to robust stability and performance analysis for systems with structured uncertainty
288
An
N
:1 time-voltage matrix encoded transmission system
289
An
N
-dimensional SIMD ring architecture for implementing very large order adaptive digital filters
290
An
O
(
kn
) algorithm for a circular consecutive-
k
-out-of-
n
:F system
291
An
O
(
kn
)-time algorithm for computing the reliability of a circular consecutive-
k
-out-of-
n
:F system
292
An
O
(
n
log
m
) algorithm for VLSI design rule checking
293
An
O
(
N
log
2
2
N
) fault-tolerant decentralized commit protocol
294
An
O
(
n
×log(
n
)) algorithm to compute the all-terminal reliability of (
K
5
,
K
2.2.2
) free networks
295
An
O
(
n
) winner-take-all circuit using successive elimination
296
An
O
(
n
1.5
log
n
) 1-d compaction algorithm
297
An
S
-dimensional assignment algorithm for track initiation
298
An
X
-band experimental model of a millimeter-wave interinjection-locked phased array system
299
An
X
-band high-efficiency MMIC power amplifier with 20-dB return losses
300
An
X
-band spacecraft transponder for deep space applications-design concepts and breadboard performance
301
An
X
-band, 2.5 watt continuous wave dielectric resonator oscillator for future military systems
302
An
I/Q
-Channel Time-Interleaved Bandpass Sigma–Delta Modulator for a Low-IF Receiver
303
An
in situ
Tunable Diode Mounting Topology for High-Power X-Band Waveguide Switches
304
An
In Vitro
Model of a Retinal Prosthesis
305
An
on
–
off
-Keying Optical Receiver With Dual Thresholds and Erasure Zone
306
An
In Situ
Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography
307
An
-Matrix-Based Integral-Equation Solver of Reduced Complexity and Controlled Accuracy for Solving Electrodynamic Problems
308
An
-Band Dual-Mode RF Receiver for GPS and Galileo in 0.18-
CMOS
309
An
Metal-Semiconductor-Metal VUV Photodetector
310
An
Shortest Path Algorithm Based on Delaunay Triangulation
311
An
Raman Shifting Driven by a Pulsed LD Pumped Nd:YAG Laser
312
An
Gradient Method for Network Resource Allocation Problems
313
An
Algorithm for the Calculation of Far Field Radiation Patterns
314
An
-Band Lumped-Element Wilkinson Combiner With Embedded Impedance Transformation
315
An
-Stable Model-Based Linear-Parameter-Varying Control for Managing Server Performance Under Self-Similar Workloads
316
An
Approach for Robust Calibration of Cascaded Sigma–Delta Modulators
317
An
-Boosting Algorithm for Estimation of a Regression Function
318
An
LPV Design for Sampling Varying Controllers: Experimentation With a T-Inverted Pendulum
319
An
-Laplace Robust Kalman Smoother
320
An
Plasma Device for Sterilization of Root Canal of Teeth
321
An
Control Strategy for Switching Converters in Sliding-Mode Current Control
322
An
-band ferrite coaxial line modulator
323
An
algorithm for partial fraction expansion
324
An
norm bound for state variables in second-order recursive digital filter
325
An
2
stability criterion with frequency domain interpretation for a class of nonlinear discrete systems
326
An
Fault Estimation Scheme of Wireless Networked Control Systems for Industrial Real-Time Applications
327
An
Adaptive Sub-Domain Framework for Parametric Order Reduction
328
An
Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-
329
An
-Time Algorithm for Detecting Superbubbles
330
An
In-Situ
Structural Health Diagnosis Technique and Its Realization via a Modularized System
331
An
LC
-Type Passive Wireless Humidity Sensor System With Portable Telemetry Unit
332
An
LCL
-
LC
Filter for Grid-Connected Converter: Topology, Parameter, and Analysis
333
An
fptas
for Response Time Analysis of Fixed Priority Real-Time Tasks with Resource Augmentation
334
An
87
Rb cold atom interferometric gravimeter
335
An
87
Sr lattice clock
336
An 0(1.414
n
) volume molecular solution for the 0–1 knapsack problem on DNA-based supercomputing
337
An 0(n) Parallel Multiplier with Bit-Sequential Input and Output
338
An 0(n
2.5
) Fault Identification Algorithm for Diagnosable Systems
339
An 0.03 μm gate-length enhancement-mode InAlAs/InGaAs/InP MODFET´s with 300 GHz f
T
and 2 S/mm extrinsic transconductance
340
An 0.1-μm asymmetric halo by large-angle-tilt implant (AHLATI) MOSFET for high performance and reliability
341
An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance
342
An 0.18 μm embedded FCRAM ASIC with DRAM density and SRAM performance
343
An 0.18μm CMOS electrochemical sensor readout IC for exhaust gas monitoring
344
An 0.18-μm CMOS for mixed digital and analog applications with zero-volt-V
th
epitaxial-channel MOSFETs
345
An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHz f
max
and 10-V BV
ceo
for RF telecommunication
346
An 0.35-μm, 6-m/spl Omega/, 43 μ/spl Omega/-cm
sub 2
lateral power MOSFET for low-voltage, megahertz switching power applications
347
An 0.35μm/ CMOS 2.4Gb/s LVDS for high-speed DAC
348
An 0.5 μm BiCMOS technology for low power wireless telecommunications applications
349
An 0.5–6GHz ultra-wideband low noise amplifier design
350
An 0.5-μm CMOS analog random access memory chip for TeraOPS speed multimedia video processing
351
An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface
352
An 0.8 µm 256K BiCMOS SRAM technology
353
An 0.8 µm CMOS technology for high performance logic applications
354
An 0.8 /spl mu/m CMOS mixed analog-digital integrated audiometric system
355
An 0.8-μm CMOS mixed analog-digital integrated audiometric system
356
An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI
357
An 0.8-mm
9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS
358
An 0.9 x 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface
359
An 0ptimal Linear Discriminant Analysis for Pattern Recognition
360
An 1 GHz All-implanted Vertical pnp Transistor
361
An 1 GHz Class E LDMOS Power Amplifier
362
An 1 GHz class E LDMOS power amplifier
363
An 1 V 6.25 GHz PLL with 0.5 ps rms Jitter in 0.13 /spl mu/m CMOS
364
An 1 V rail-rail low-power CMOS op-amp
365
An 1 V–1 nW source follower ISFET readout circuit for biomedical applications
366
An 1μm all-fiber based pulsed laser system incorporating an agile waveform tailoring driver
367
An 1.1-GHz packaged CMOS VCO with phase noise of -126 dBc/Hz at a 600-kHz offset
368
An 1.2 V 8-bit 1-MS/s single-input res-cap segment SAR ADC for temperature sensor in LTE
369
An 1.25 Gbit/s -29 dBm burst-mode optical receiver realized with 0.35 μm SiGe BiCMOS process using a PIN photodiode
370
An 1.2V 440-MS/s 0.13-µm CMOS pipelined Analog-to-Digital Converter with 5-8bit mode selection
371
An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm
372
An 1.5 V Cyclic A/D Converter in Standard CMOS Technology
373
An 1.61mW mixed-signal column processor for BRISK feature extraction in CMOS image sensor
374
An 1.92mW Feature Reuse Engine based on inter-frame similarity for low-power object recognition in video frames
375
An 10 nV/√Hz JFET input precision operational amplifier
376
An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector
377
An 10-Gb/s pulse-mode I/O for on-chip 5-mm interconnect
378
An 11
w, two-electrode transimpedance biosignal amplifier with active current feedback stabilization
379
An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space
380
An 11 bit SAR ADC combining a split capacitor array with a resistive ladder and a configurable noise time domain comparator
381
An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply Voltage
382
An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique
383
An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 6Snm CMOS
384
An 11 Gbit/s, 151 km transmission experiment employing a 1480 nm pumped erbium-doped in-line fiber amplifier
385
An 11 GHz 3-V SiGe voltage controlled oscillator with integrated resonator
386
An 11 GHz Contiguous Band Output Multiplexing Network for INTELSAT VI Spacecraft
387
An 11 GHz dual-beamwidth slant-path attenuation experiment carried out at Martlesham Heath, UK
388
An 11 GHz FPGA with test applications
389
An 11 GHz High Capacity Digital Radio System for Overlaying Existing Microwave Routes
390
An 11 GHz photonic band gap accelerator structure with wakefield suppression
391
An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS
392
An 11 kV steady state residential aggregate load model. Part 1: Aggregation methodology
393
An 11 kV steady state residential aggregate load model. Part 2: Microgeneration and demand-side management
394
An 11 mm
, 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12
395
An 11 W Ku-band heterostructure FET with WSi/Au T-shaped gate
396
An 11%-Power-Conversion-Efficiency Organic–Inorganic Hybrid Solar Cell Achieved by Facile Organic Passivation
397
An 11–18 GHz four-channel DBR multiplexer for electronic warfare systems
398
An 11,000-Mc Radio System Across Chesapeake Bay
399
An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture
400
An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI
401
An 11,424-gate dynamic optically reconfigurable gate array VLSI
402
An 11.1 Gb/s WDM/TDM-PON system with 100 km reach using ultra-low loss fiber and duobinary downstream signals
403
An 11.1 Gbps Analog PRML Receiver for Electronic Dispersion Compensation of Fiber Optic Communications
404
An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18
m CMOS
405
An 11.1Gbps analog PRML receiver for EDC of up to 400km-reach WDM fiber-optic links
406
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator
407
An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS
408
An 11.5% frequency tuning, −184 dBc/Hz noise FOM 54 GHz VCO
409
An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS
410
An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation
411
An 11.7–17.2GHz digitally-controlled oscillator in 65nm CMOS for high-band UWB applications
412
An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOS
413
An 11.8-Ghz 31-mW CMOS Frequency Divider
414
An 11/19-GHz VCO using switchable transformer in 0.18-µm CMOS
415
An 11000-fuse electrically erasable programmable logic device (EEPLD) with an extended macrocell
416
An 1152 channel singles list-mode data acquisition system for MADPET-II
417
An 118dB DR CT IF-to-Baseband /spl Sigma//spl Delta/ Modulator for AM/FM/IBOC Radio Receivers
418
An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals
419
An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS
420
An 11b 300MS/s 0.24pJ/conversion-step Double-Sampling Pipelined ADC with on-chip full digital calibration for all nonidealities including memory effects
421
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects
422
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H
423
An 11b 70 MHz 1.2 mm
2
49mW 0.18 um CMOS ADC with on-chip current/voltage references
424
An 11b 70-MHz 1.2-mm
2
49-mW 0.18-μm CMOS ADC with on-chip current/voltage references
425
An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration
426
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC
427
An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals
428
An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals
429
An 11-Band 3–10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication
430
An 11-Band 3.4 to 10.3 GHz MB-OFDM UWB Receiver in 0.25/spl mu/m SiGe BiCMOS
431
An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system
432
An 11-bit 200MS/s SAR ADC IP for wireless comunacation SOC
433
An 11-Bit 330MHz 8X OSR /spl Sigma/-spl Delta/ Modulator for Next-Generation WLAN
434
An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage
435
An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage
436
An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC
437
An 11-bit 8.6GHz direct digital synthesizer MMIC with 10-bit segmented nonlinear DAC
438
An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments
439
An 11-bit high-speed current steering DAC
440
An 11-bit Two-Stage Hybrid-DAC for TFT LCD Column Drivers
441
An 11-bits 50 kSamples/s Switched-Current DA converter
442
An 11-Cryotron Full Adder
443
An 11-Cryotron Full Adder
444
An 11-fs, 5-kHz optical parametric/Ti:sapphire hybrid chirped pulse amplification system
445
An 11Gb/s CMOS Demultiplexer Using Redundant Multi-valued Logic
446
An 11Gb/s Inductive-Coupling Link with Burst Transmission
447
An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS
448
An 11-GHz 3-V SiGe voltage-controlled oscillator with integrated resonator
449
An 11-GHz GaAs frequency divider using source-coupled FET Logic
450
An 11-GHz multi-beam dielectric rod antenna using non-planar array approach
451
An 11k-Electrode 126-Channel High-Density Microelectrode Array to Interact with Electrogenic Cells
452
An 11-Mb/s 2.1-mW Synchronous Superregenerative Receiver at 2.4 GHz
453
An 11-million Transistor Neural Network Execution Engine
454
An 11mm
2
70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOS
455
An 11M-triangles/sec 3D graphics clipping engine for triangle primitives
456
An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing
457
An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS
458
An 11ns 8k x 18 Cmos Static Ram
459
An 11-ns 8K×18 CMOS static RAM with 0.5-μm devices
460
An 11-stage ring oscillator with nonlinear negative feedback for high speed digital applications
461
An 11-tap 0.9-μm CMOS digital transversal equalizer for digital radio
462
An 17/8-IPS magnetic recording system for stereophonic music
463
An 18 b 10 mu s self-calibrating ADC
464
An 18 b 12.5 MS/s ADC With 93 dB SNR
465
An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range
466
An 18 Channel, Phase-Matched, Single-Conversion Upconverter from 30MHz to L-Band
467
An 18 element strip of 1 mm
2
G-APDs for CMS HCAL upgrade results of CERN test beam 2009
468
An 18 GHz 8-way Radial Combiner
469
An 18 GHz Bandwidth, 60 GS/s Sample Rate Real-time Waveform Digitizing System
470
An 18 GHz circularly polarised multilayer active microstrip antenna subarray using MMIC amplifiers
471
An 18 GHz circularly polarised multilayer active microstrip antenna subarray using MMIC amplifiers
472
An 18 GHz continuous time /spl Sigma/-/spl Delta/ modulator implemented in InP transferred substrate HBT technology
473
An 18 GHz Double-Tuned Parametric Amplifier
474
An 18 GHz low noise high linearity active mixer in SiGe
475
An 18 GHz Si bipolar mold package prescaler
476
An 18 GHz Si bipolar mold package prescaler
477
An 18 GHz Single-Tuned Parametric Amplifier with Large Gain Bandwidth Product (Correspondence)
478
An 18 GHz-band MMIC linearizer using a parallel diode with a bias feed resistance and a parallel capacitor
479
An 18 Mb, 12.3 GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin
480
An 18 mW 1800 MHz quadrature demodulator in 0.18 /spl mu/m CMOS
481
An 18 ns 4Kx4 CMOS SRAM
482
An 18 ns 56-bit multiply-adder circuit
483
An 18 ns CMOS/SOS 4K static RAM
484
An 18 to 26.5 GHz Waveguide Load-Pull System Using Active-Load Tuning
485
An 18 to 33 GHz Fully-Integrated Darlington Power Amplifier With Guanella-Type Transmission-Line Transformers in 0.18
CMOS Technology
486
An 18 to 40GHz Double Balanced Mixer MMIC
487
An 18 to 40GHz Double Balanced Mixer MMIC
488
An 18 to 40GHz double balanced MMIC mixer using GaAs technology
489
An 18µW 79dB-DR 20KHz-BW MASH ΔΣ modulator utilizing self-biased amplifiers for biomedical applications
490
An 18–32 GHz ultra wideband low-noise amplifier with a low variation of group delay
491
An 18–40 GHz ultra broadband low noise amplifier MMIC
492
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode
493
An 18.5ns 128MB SOI DRAM with a floating body cell
494
An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication
495
An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip
496
An 18.7mW 10-GHz Phase-Locked Loop Circuit in 0.13-µm CMOS
497
An 180 MHz 16 bit multiplier using asynchronous logic design techniques
498
An 180 nm CMOS single inverter 2.4 GHz LC oscillator
499
An 1800 V 300 A nondestructive tester for bipolar power transistors
500
An 1800 V triple implanted vertical 6H-SiC MOSFET
501
An 180nm CMOS Low Noise Amplifier with single ended input and differential output: RF and Non linear signal processing
502
An 18-20 GHz Subharmonic Satellite Down-Converter in 0.18μm SiGe Technology
503
An 18-21 GHz InP DHBT linear microwave Doherty amplifier
504
An 18-22-GHz down-converter based on GaAs/AlGaAs HBT-Schottky diode integrated technology
505
An 18-34 GHz dynamic frequency divider based on 0.2 mu m AlGaAs/GaAs/AlGaAs quantum-well transistors
506
An 18-34-GHz dynamic frequency divider based on 0.2-μm AlGaAs/GaAs/AlGaAs quantum-well transistors
507
An 18-40 GHz Double Balanced Microstrip Mixer
508
An 18-40 GHz monolithic ring mixer
509
An 18-40 GHz phase locked downconverter subsystem
510
An 18-71 GHz multi-band and high gain GaAs MMIC medium power amplifier for millimeter-wave applications
511
An 18b 12.5MHz ADC with 93dB SNR
512
An 18b 20KHz Dual /spl Sigma/spl Delta/ A/D Converter
513
An 18b Oversampling A/D Converter for Digital Audio
514
An 18-bit DAC for consumer applications
515
An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM
516
An 18-channel multifrequency laser
517
An 18dBm transmitter frontend with 29% PAE for 24GHz FMCW radar applications
518
An 18Gb/s duobinary receiver with a CDR-assisted DFE
519
An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70–80 GHz Band
520
An 18-GHz 300-mW SiGe power HBT
521
An 18-GHz continuous-time Σ-Δ analog-digital converter implemented in InP-transferred substrate HBT technology
522
An 18-GHz Double-Tuned Parametric Amplifier
523
An 18Ghz LNA Ga FET high gain amplifier for WLAN
524
An 18-GHz, 10.9-dBm fully-integrated power amplifier with 23.5% PAE in 130-nm CMOS
525
An 18K bipolar dynamic random access memory
526
An 18K Bipolar Dynamic Random Access Memory Chip
527
An 18mb Serial Flash Eeprom For Solid-state Disk Applications
528
An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin
529
An 18ms-latency wireless high quality codec SoC for full HD streaming
530
An 18-mW 1.175–2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners
531
An 18mW 1800MHz quadrature demodulator in 0.18/spl mu/m CMOS
532
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with < 10-Hz RF carrier resolution
533
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution
534
An 18mW 90 to 770MHz synthesizer with agile auto-tuning for digital TV-tuners
535
An 18-mW two-stage CMOS transimpedance amplifier for 10 Gb/s optical application
536
An 18-ns 1-Mbit CMOS SRAM
537
An 18ns CMOS/SOS 4K static RAM
538
An 18ns1mh Cmos Sram
539
An 18-Pulse AC-DC Converter for Power Quality Improvement in Vector Controlled Induction Motor Drives
540
An 18V double level poly CMOS technology for nonvolatile memory and linear applications
541
An 1Ã\x97(2N+1) MMI Optical Splitters Based on SOI Rib Waveguide
542
An 1-DOF controlled attraction type magnetic bearing
543
An 1-GHz CMOS voltage-controlled oscillator
544
An 1-V wide-linear-range weak inversion operational transconductance amplifier for low power applications
545
An 1-V, 74-dB, sub-Hz G
m
-C filter based on a modular transconductance reduction technique
546
An 32-kbps ADPCM encoding with a variable initially large leakage and adaptive dual loop predictors
547
An 3D interactive virtual reality software toolkit for minimally invasive vascular surgery
548
An 64-80-96 kbit/s scalable wideband speech coding candidate for ITU-T G.711-WB standardization
549
An 8 µm period bubble memory device with relaxed function designs
550
An 8 × 8 sub-threshold digital CMOS carry save array multiplier
551
An 8 – 18 GHz wideband SiGe BiCMOS low noise amplifier
552
An 8 × 8 Pixel Array Pen-Input OLED Screen Based on Organic Magnetoresistance
553
An 8
2.5 W 1%-THD 104 dB(A)-Dynamic-Range Class-D Audio Amplifier With Ultra-Low EMI System and Current Sensing for Speaker Protection
554
An 8 b 100 MSample/s CMOS pipelined folding ADC
555
An 8 b 40 MHz CMOS subranging ADC with pipelined wideband S/H
556
An 8 b 500 MS/s full Nyquist cascade A/D converter
557
An 8 b 52 MHz double-channel CMOS A/D converter for high-speed data communications
558
An 8 b 650 MHz folding ADC
559
An 8 b 800 MHz D/A converter
560
An 8 b CMOS vector A/D converter
561
An 8 b fuzzy coprocessor for fuzzy control
562
An 8 b resolution 360 /spl mu/s write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS)
563
An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS
564
An 8 Bit 10 GS/s 2Vpp Track and Hold Amplifier in SiGe BiCMOS Technology
565
An 8 bit 100 MHz 3 channel CMOS DAC with analog switching current cells
566
An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output
567
An 8 Bit 4 GS/s 120 mW CMOS ADC
568
An 8 bit microprocessor identifies second order transfer functions
569
An 8 bit presettable/programmable synchronous counter/divider
570
An 8 bit programmable 18 GHz frequency divider for mm-wave frequency synthesis
571
An 8 bit, 100 ms/s flash ADC
572
An 8 bit, 200 MHz BiCMOS comparator
573
An 8 bit, 200Ms/s, full Nyquist, 3.3V, differential interpolated flash A/D converter in BiCMOS technology
574
An 8 channel 8b µ P compatible NMOS converter with programmable ranges
575
An 8 cm Period Electromagnetic Wiggler Magnet with Coils Made from Sheet Copper
576
An 8 element broadband antenna for AMPS+GSM applications
577
An 8 G connections-per-second 54 mW digital neural network chip low-power chain-reaction architecture
578
An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology
579
An 8 Gb/s QPSK optical homodyne detection experiment using external-cavity laser diodes
580
An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS
581
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme
582
An 8 Gbit/s-76 km transmission experiment using a distributed feedback laser at 1.3 μm wavelength
583
An 8 Gbps fast-locked automatic gain control for PAM receiver
584
An 8 Gbps, 4:1 transition-aware self-toggling multiplexer
585
An 8 GEV H- multi-turn injection system for the Fermilab Main Injector
586
An 8 GHz array of circularly polarised, dual mode patches suitable for space deployment
587
An 8 GHz CMOS near field bio-sensor array for imaging spatial permittivity distribution of biomaterials
588
An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation
589
An 8 Ghz MMIC Preamplifier
590
An 8 GHz silicon bipolar clock-recovery and data-regenerator IC
591
An 8 GHz ultra wideband transceiver prototyping testbed
592
An 8 GHz Variable Gain Low Noise Amplifier (VGLNA) Utilizing Parallel Inter-Stage Resonance
593
An 8 kb/s low complexity ACELP speech codec
594
An 8 kb/s low-delay CELP speech coder
595
An 8 Kb/s low-delay CELP speech coder
596
An 8 kbit/s ACELP coder with improved background noise performance
597
An 8 kbit/s LD-CELP with improved excitation and perceptual modelling
598
An 8 kbit/s transform coder for noisy channels
599
An 8 kbps TC-MQ (time domain compression ADPCM-MQ) speech codec
600
An 8 mA, 3.8 dB NF, 40 dB gain CMOS front-end for GPS applications
601
An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput
602
An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management
603
An 8 Mbit DRAM design using a 1 Tbulk cell
604
An 8 Mbps data rate transmission by inductive link dedicated to implantable devices
605
An 8 MBYTE magnetic bubble memory
606
An 8 megapixel/sec 800 × 800 virtual phase CCD imager scientific applications
607
An 8 MHz, 80 Ms/s switched-current filter
608
An 8 mm FM and AM noise measuring equipment
609
An 8 mm length nonblocking 4×4 optical switch array
610
An 8 mm/sup 2/, 5 V 16K dynamic RAM using a new memory cell"
611
An 8 mm
3
digitally steered laser beam transmitter
612
An 8 mm-waveband wattmeter
613
An 8 ns 1 Mb ECL BiCMOS SRAM
614
An 8 ns 256 K BiCMOS RAM
615
An 8 ns 4 Mb serial access memory
616
An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size
617
An 8 ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D/sup 2/ RAM)
618
An 8 T Superconducting Split Magnet System With Large Crossing Warm Bore
619
An 8 to 9 GHz LC-VCO and harmonic-suppressed CML divider with low supply voltage for FMCW synthesizer
620
An 8 W GaAs Class-AB amplifier for operation in envelope tracking systems
621
An 8" Fab Startup: Motorola MOS 11
622
An 8×10
5
bit bubble memory cell for spacecraft applications
623
An 8μW Heterodyning Chopper Amplifier for Direct Extraction of 2μV
rms
Neuronal Biomarkers
624
An 8×10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
625
An 8×16-pixel 92kSPAD time-resolved sensor with on-pixel 64ps 12b TDC and 100MS/s real-time energy histogramming in 0.13µm CIS technology for PET/MRI applications
626
An 8×1k SPAD detector with TDI in 0.13μm CMOS technology
627
An 8×8 broadcast-and-select optical switch based on monolithically integrated EAM-gate array
628
An 8×8 Butler matrix for generation of waves carrying Orbital Angular Momentum (OAM)
629
An 8×8 CMOS microelectrode array for electrochemical dopamine detection
630
An 8×8 FPGA-based MIMO-OFDM real-time transmission testbed: OGNO implementation and experimental results
631
An 8×8 lightweight flexible multilayer antenna array
632
An 8×8 MIMO 3-axis weighted polarization active antenna for wearable radio applications
633
An 8×8 RLS based MIMO detection ASIC for broadband MIMO-OFDM wireless transmissions
634
An 8×8 row-column summing readout electronics for preclinical positron emission tomography scanners
635
An 8×8 run-time reconfigurable FPGA embedded in a SoC
636
An 8Ω 2.5W 1%-THD 104dB(A)-dynamic-range Class-D audio amplifier with an ultra-low EMI system and current sensing for speaker protection
637
An 8Ω, 1.75W, 95% efficiency, 0.004% THD+N Class-D amplifier with a feed-forward ADC and feedback filters
638
An 8μW 100kS/s successive approximation ADC for biomedical applications
639
An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”
640
An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning
641
An 8–16 GHz SiGe Low Noise Amplifier With Performance Tuning Capability for Mitigation of Radiation-Induced Performance Loss
642
An 8–18 GHz Low noise amplifier design in 0.18μm CMOS technology
643
An 8–18GHz 0.18W wideband recursive receiver MMIC with gain-reuse
644
An 8∼20GHz wideband frequency synthesizer
645
An 8×1 micromachined micro-Fresnel lens array for free-space optical interconnect
646
An 8×8 adiabatic quasi-static CMOS multiplier
647
An 8×8 discrete cosine transform chip with pixel rate clocks
648
An 8×8 discrete cosine transform model using VHDL
649
An 8×8 pixel array IC for X-ray spectroscopy
650
An 8×8 pixel IC for X-ray spectroscopy
651
An 8×8-block based motion estimation using Kalman filter
652
An 8*8 ATM switch LSI with shared multi-buffer architecture
653
An 8,500-hp gas-turbine-electric locomotive
654
An 8.0 Watt K-Band FET Amplifier for Satellite Downlink
655
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors
656
An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and −98 dB THD
657
An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and
98 dB THD
658
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme
659
An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS
660
An 8.2 GHz triple coupling low-phase-noise class-F QVCO in 65nm CMOS
661
An 8.2 J phase-conjugate solid-state laser coherently combining eight parallel amplifiers
662
An 8.2 J solid-state laser using phase-conjugation to coherently combine eight parallel amplifiers
663
An 8.2 to 20.1 GHz LC PLL with Sub-100 fs Jitter in 0.13 µm SiGe BICMOS
664
An 8.29 mm
52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13
m CMOS Process
665
An 8.2-GHz, 14.4mW, 1.6dB NF SiGe bipolar LNA with DC current reuse
666
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS
667
An 8.3-GHz dual-modulus divide-by-31/32 prescaler using enhanced phase switching
668
An 8.4 GHz SiGe/Si HBT-based MMIC power amplifier
669
An 8.4-12.0 GHz down-conversion mixer implemented in SiGe HBT technology
670
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling
671
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology
672
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme
673
An 8.5 GHz SiGe-based amplifier using fully self-aligned double mesa SiGe HBTs
674
An 8.5 mW Continuous-Time
Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR
675
An 8.5 mW, 0.07 mm
2
ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter
676
An 8.5–10.0 GHz 310 W GaN HEMT for radar applications
677
An 8.5–11.5Gbps SONET transceiver with referenceless frequency acquisition
678
An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition
679
An 8.5Gb/s CMOS OEIC with on-chip photodiode for short-distance optical communications
680
An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer
681
An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS
682
An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI
683
An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit
684
An 8.5-ns 112-bit transmission gate adder with a conflict-free bypass circuit
685
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement
686
An 8.6 MHz extended cavity femtosecond Cr:LiSAF laser pumped by single spatial mode diodes
687
An 8.6 mW 25 Mvertices/s 400-MFLOPS 800-MOPS 8.91 mm
Multimedia Stream Processor Core for Mobile Applications
688
An 8.6 um2 cell technology for a 35.5 mm2 megabit EPROM
689
An 8.61 Tflop/s Molecular Dynamics Simulation for NaCl with a Special-Purpose Computer: MDM
690
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics
691
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics
692
An 8.6GHz 42ps pulse-width electrical mode-locked oscillator
693
An 8.6mW 12.5Mvertices/s 800MOPS 8.91mm
2
Stream Processor Core for Mobile Graphics and Video Applications
694
An 8.7 GHz Si photodiode in standard 0.18-μm CMOS technology
695
An 8.7–13.8 GHz transformer-coupled varactor-less quadrature current-controlled oscillator RFIC
696
An 8.8 GHz resonator based on multi-walled aligned carbon nanotube array
697
An 8.8–9.8 GHz 100W hybrid solid state power amplifier for high power applications
698
An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS
699
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture
700
An 8.9mW 25Gb/s inductorless 1:4 DEMUX in 90nm CMOS
701
An 8/4-bit reconfigurable digital pixel array with on-chip non-uniform quantizer
702
An 8/9 rate time-varying trellis code for high density magnetic recording
703
An 8/9 Rate Time-varying Trellis Code For High Density Magnetic Recording
704
An 8/spl times/8 array of resonant cavity enhanced light emitting diodes integrated onto silicon grayscale (32 level) driver circuitry
705
An 8/spl times/8 array of surface emitting lasers with heterojunction bipolar transistors integrated on them
706
An 8/spl times/8-b nRERL serial multiplier for ultra-low-power applications
707
An 8?12G PA driver amplifier using 0.18 ?m BiCMOS technology with 19.4dBm outputpower
708
An 8?ƒ\x978 Quasi-Orthogonal STBC form for transmissions over eight or four antennas
709
An 8
8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-
5 Gb/s Parallel Receiver With Collaborative Timing Recovery
711
An 8
8 Butler Matrix in 0.13-
CMOS for 5–6-GHz Multibeam Applica
712
An 8
$\,\times\,$
8 InP Monolithic Tunable Optical Router (MOTOR) Packet Forwarding Chip
713
An 8
th
sub-harmonic injection locked V-band VCO for low power LO routing in mm-wave beamformers
714
An 8
th
-order MASH delta-sigma with an OSR of 3
715
An 80 b, 6.7 MFLOPS floating-point processor with vector/matrix instructions
716
An 80 Gbit/s 1:2 demultiplexer in InP-based HEMT technology
717
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller
718
An 80 GHz High Gain Double-Balanced Active Up-Conversion Mixer Using 0.18
SiGe BiCMOS Technology
719
An 80 GHz programmable frequency divider for wideband mm-Wave frequency ramp synthesis
720
An 80 GHz radar level measurement system with dielectric lens antenna
721
An 80 GHz SiGe Bipolar VCO with Wide Tuning Range Using Two Simultaneously Tuned Varactor Pairs
722
An 80 GHz SiGe Quadrature Receiver Frontend
723
An 80 GHz Wide Tuning Range Push-Push VCO With
-Boosted Full-Wave Rectification Technique in 90 nm CMOS
724
An 80 kG-Foot Beam Switching Magnet and Its Pulsed Current Supply
725
An 80 k-transistor configurable 25 MPixels/s video compression processor unit
726
An 80 Mb/s adaptive DFE detector in 1 /spl mu/m CMOS [hard-disk drives]
727
An 80 MFLOPS floating-point engine in the Intel i860 processor
728
An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection
729
An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing
730
An 80 MHz 8th-order bandpass ΔΣ-modulator with a 75 dB SNDR for IS-95
731
An 80 MHz digital signal processing multichip module made with the General Electric high density interconnect technology
732
An 80 Mhz Mips R6000 Cpu Using Multi Chip Module Technology
733
An 80 MHz noise optimized continuous-time bandpass filter in 0.25 μm BiCMOS
734
An 80 mm/sup 2/ MPEG2 audio/video decode LSI
735
An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection
736
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface
737
An 80 mW 40 Gb/s 7-Tap
T
/2-Spaced Feed-Forward Equalizer in 65 nm CMOS
738
An 80 mW dual video-codec SoC for seamless playback of digital terrestrial television and mobile broadcasting services
739
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion
740
An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE
741
An 80 nm In
0.7
Ga
0.3
As MHEMT with flip-chip packaging for W-band low noise applications
742
An 80 nm ultra wide band EDFA with low noise figure and high output power
743
An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller
744
An 80 ns 1 Mbit MASK ROM with a new memory cell
745
An 80 ns 32K EEPROM using the FETMOS cell
746
An 80 ps ECL circuit with high current density transistor
747
An 80 W - Solid-State Microwave Source for the Excitation of Electrodeless Lamps
748
An 80 Watt dual Ka/Q-band mini-TWT
749
An 80% peak efficiency, 0.84mW sleep power consumption, fully-integrated DC-DC converter with buck/LDO mode control
750
An 80% peak efficiency, 410mW, single supply rail powered Class-I linear audio amplifier
751
An 80% power efficient, 125-Watt, GaN-based RF power amplifier designed for continuous duty and linear operation on L-band
752
An 80×60 range image sensor based on 10µm 50MHz lock-in pixels in 0.18µm CMOS
753
An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology
754
An 80μV
rms
-temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC
755
An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers
756
An 80/160 GHz broadband, fixed-tuned, balanced frequency doubler
757
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications
758
An 800 bit/s vector quantization LPC vocoder
759
An 800 bps adaptive vector quantization vocoder using a perceptual distance measure
760
An 800 Bps real-time voice coding system based on efficient encoding techniques
761
An 800 GHz NbN phonon-cooled hot-electron bolometer mixer receiver
762
An 800 Mb/s physical layer LSI with hybrid port architecture for consumer electronics networking
763
An 800 Mbit/s optical transmission experiment using a single-mode fiber
764
An 800 Mbps multi-channel CMOS serial link with 3× oversampling
765
An 800 Mbps system interconnect modeling and simulation for high speed computing
766
An 800 MHz 0.35 μm CMOS clock tree and PLL based on a new charge-pump circuit
767
An 800 MHz 1-micron CMOS pipelined 8-bit adder using true single-phase logic-flip-flops
768
An 800 MHz 2
1 Compact MIMO Antenna System for LTE Handsets
769
An 800 MHz Adjustment-Free Multistage MIC Power Amplifier
770
An 800 MHz band high-efficiency power amplifier microwave integrated circuit
771
An 800 MHz HBT class-E amplifier with 74% PAE at 3.0 volts for GMSK
772
An 800 MHz Low Power Consumption Frequency Synthesizer using Intermittent Operation of a Modified PLL Circuit with Dual Loops
773
An 800 MHz monolithic GaAs HBT serrodyne modulator
774
An 800 MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 /spl mu/m CMOS
775
An 800 MHz-band front-end MCM for antenna diversity type mobile communication handset terminals
776
An 800 MOPS 110 mW 1.5 V parallel DSP for mobile multimedia processing
777
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS
778
An 800 MSPS quadrature DDFS and integrated nonlinear DAC-filter with <15 ns instantaneous frequency hopping time
779
An 800 MSps track and hold using a 0.3 /spl mu/m AlGaAs-HEMT-technology
780
An 800 mW 10 Gb Ethernet transceiver in 0.13 μm CMOS
781
An 800 volts high voltage interconnection level shifter using Floating Poly Field Plate (FPFP) method
782
An 800-μW H.264 Baseline-Profile Motion Estimation Processor Core
783
An 800-/spl mu/W 26-GHz CMOS tuned amplifier
784
An 800Mb/s physical layer LSI with hybrid port architecture for consumer electronics networking
785
An 800-MeV Spin Precessor for Polarized H- Beams Using H- to Ho Stripping
786
An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops
787
An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL
788
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms
789
An 800Mhz cryptographic pairing processor in 65nm CMOS
790
An 800MHz embedded DRAM with a concurrent refresh mode
791
An 800-MHz embedded DRAM with a concurrent refresh mode
792
An 800-MHz insulated gate buried-channel CCD on InP
793
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter
794
An 800-MHz monolithic GaAs HBT serrodyne modulator
795
An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS
796
An 800MHz star-connected on-chip network for application to systems on a chip
797
An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS
798
An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS
799
An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing
800
An 800MS/s dual-residue pipeline ADC in 40nm CMOS
801
An 800mW fully-integrated 130nm CMOS DC-DC step-down multi-phase converter, with on-chip spiral inductors and capacitors
802
An 800V integrated DMOS-IGBT/PiN or MPS-rectifier power device
803
An 800-Watts Power Solution Module for L-band Pulsed Radar Applications
804
An 80-120 GHz Sub-Harmonically Pumped Image-Reject Integrated Circuit Mixer
805
An 802.11 Based Location-Aware Computing: Intelligent Guide System
806
An 802.11 Based MAC Protocol for Providing QoS to Real Time Applications
807
An 802.11a/b/g RF Transceiver in an SoC
808
An 802.11-Based MAC Protocol for Reliable Multicast in Multihop Networks
809
An 802.11g WLAN SoC
810
An 802.11g WLAN SoC
811
An 802.11n/satellite 2-in-1 OFDM-based transport architecture for seamless mobile telemedicine
812
An 802.15.4a wide band frequency synthesizer for 5GHz ISM band health care applications
813
An 805 MHz high-power klystron
814
An 805 MHz high-power klystron
815
An 805-Mc 1-1/4-Mw Amplifier for Acceierator Service
816
An 8085 based STD bus system for digital control applications
817
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT
Modulator Dissipating 13.7-mW
818
An 80-dB linear baseband CMOS VGA with temperature compensation for low-power application
819
An 80-dB SNR 4th-order discrete-time sigma-delta modulator
820
An 80-Fold Speedup, 15.0 TFlops Full GPU Acceleration of Non-Hydrostatic Weather Model ASUCA Production Code
821
An 80-Gb/s 2.7-V
p-p
driver IC based on functional distributed circuits for optical transmission systems
822
An 80-Gb/s 2
31
-1 pseudorandom binary sequence generator in SiGe BiCMOS technology
823
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs
824
An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode
825
An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs
826
An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs
827
An 80-GHz chirp-free carrier-suppressed optical pulse generator using cascaded 20-GHz clock-driven Mach-Zehnder modulators
828
An 80-GHz low noise amplifier resilient to the TX-spillover in phase-modulated continuous-wave radars
829
An 80GHz range synchronized push-push oscillator for automotive radar application
830
An 80GHz travelling-wave amplifier in a 90nm CMOS technology
831
An 80-GW relativistic electron beam accelerator
832
An 80-km-reach centralized-light-source WDM PON utilizing Inverse-RZ-Duobinary downstream signals
833
An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32,8,10) LDPC code
834
An 80-MFLOPS (peak) 64-b microprocessor for parallel computer
835
An 80MHz 4× oversampled cascaded ΔΣ-pipelined ADC with 75dB DR and 87dB SFDR
836
An 80MHz 8b CMOS D/A converter
837
An 80-MHz 8-bit CMOS D/A converter
838
An 80MHz bipolar dot rate generator
839
An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing
840
An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor
841
An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure
842
An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOS
843
An 80-Nanosecond plated-wire store for a time-compression multiplex transmission system
844
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion
845
An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller
846
An 80ns 1Mb ROM
847
An 80ns address-date multiplex 1mb CMOS EPROM
848
An 80-NS NDRO ferrite core memory design
849
An 80-NS plated-wire store for a time compression multiplex transmission system
850
An 80ps 2500-gate bipolar macrocell array
851
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
852
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
853
An 80V class Silicon Lateral Trench Power MOSFET for High Frequency Switching Applications
854
An 80W AlGaN/GaN heterojunction FET with a field-modulating plate
855
An 80-W packaged GaN high power amplifier for CW operation in the 13.75–14.5 GHz band
856
An 81 GHz, 470 mW, 1.1 mm
2
InP HBT power amplifier with 4∶1 series power combining using sub-quarter-wavelength baluns
857
An 81 MHz IF receiver in CMOS
858
An 81 MHz, 1280 × 720pixels × 30frames/s MPEG-4 video/audio CODEC processor
859
An 81.6
FastICA Processor for Epileptic Seizure Detection
860
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory
861
An 8100 pixel optoelectronic array for optogenetic retinal prosthesis
862
An 8-10-bit, 1-40 MHz analog signal processor with configurable performance for electronic imaging applications
863
An 8-12 GHz 1 Watt GaAs FET Amplifier for TWT Replacement
864
An 8-12 Kbit/S Embedded CELP Coder Interoperable with ITU-T G.729 CIDER: First Stage of the New G.729.1 Standard
865
An 8-12GHz capacitive power sensor based on MEMS cantilever beam
866
An 8-15 GHz GaAs monolithic frequency converter
867
An 8-15 GHz GaAs Monolithic Frequency Converter
868
An 8-15 GHz GaAs Monolithic Frequency Converter
869
An 8-18 GHz FET YIG-Tuned Oscillator
870
An 8-18 GHz Monolithic Two-Stage Low Noise Amplifier
871
An 8-18-GHz all-optical microwave downconverter with channelization
872
An 8-18-GHz YIG-Tuned FET Oscillator
873
An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate
874
An 8192-bit shift register
875
An 8192-channel Grating Light Valve for Ultra-Violet Direct Write lithography
876
An 8192-point fast fourier transform 3D-IC case study
877
An 81Gb/s, 1.2V TIALA-Retimer in Standard 65nm CMOS
878
An 81-Gc/s zero-field maser
879
An 81-MHz IF receiver in CMOS
880
An 82 dB CMOS continuous-time complex bandpass sigma-delta ADC for GSM/EDGE
881
An 82 to 84 percent efficient, small size, 2 and 4 stage depressed collector for octave bandwidth high performance TWT´s
882
An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors
883
An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors
884
An 82μA/MHz microcontroller with embedded FeRAM for energy-harvesting applications
885
An 82.4% efficiency package-bondwire-based four-phase fully integrated buck converter with flying capacitor for area reduction
886
An 820 pin PGA for ultra large-scale BiCMOS devices
887
An 820 pin PGA for ultralarge-scale BiCMOS devices
888
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
889
An 8-20-GHz wide-band LNA design and the analysis of its input matching mechanism
890
An 83 Ah Ni-H
2
battery for geosynchronous satellite applications
891
An 83% enhancement in the external quantum efficiency of ultraviolet flip-chip light-emitting diodes with the incorporation of a self-textured oxide mask
892
An 83% peak efficiency and 1.07W/mm
2
power density Single Inductor 4-Output DC-DC converter with Bang-Bang Zero
th
-Order Control
893
An 83.4% Peak Efficiency Single-Inductor Multiple-Output Based Adaptive Gate Biasing DC-DC Converter for Thermoelectric Energy Harvesting
894
An 830mW, 586kbps 1024-bit RSA chip design
895
An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin
896
An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin
897
An 833-MHz 132-phase multiphase clock generator with self-calibration circuits
898
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications
899
An 835kb Video Serial Memory
900
An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage
901
An 83-GHz High-Gain SiGe BiCMOS Power Amplifier Using Transmission-Line Current-Combining Technique
902
An 84 dB-gain-range and 1 GHz-bandwidth variable gain amplifier using gain flattening capacitors for multi-gigabit radio
903
An 84 GHz Bandwidth and 20 dB Gain Broadband Amplifier in SiGe Bipolar Technology
904
An 84 GHz Bandwidth and 20 dB Gain Broadband Amplifier in SiGe Bipolar Technology
905
An 84 mW 0.36 mm
2
analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS
906
An 84 pW/Frame Per Pixel Current-Mode CMOS Image Sensor With Energy Harvesting Capability
907
An 84.7% Efficiency 100-MHz Package Bondwire-Based Fully Integrated Buck Converter With Precise DCM Operation and Enhanced Light-Load Efficiency
908
An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13
m CMOS
909
An 84-dB extended dynamic range, 152fps, 512 × 384 segmented-base CMOS image sensor with a 10bit, 2.5-MS/s, 6.5-mW pipelined ADC
910
An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications
911
An 85 Ghz Quasioptical Gyroklystron
912
An 85 MHz IF bandpass sigma-delta modulator for CDMA receivers
913
An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC
914
An 85 ns 16 Mb CMOS EPROM with alterable word organization
915
An 85–115 GHz SIS Mixer Demonstrating Nearly Constant Dynamic Resistance
916
An 85–225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS
917
An 85–95.2 GHz transformer-based injection-locked frequency tripler in 65nm CMOS
918
An 85?115 GHz MMIC amplifier using self-designed 90-nm InP PHEMT
919
An 850 MHz current feedback operational amplifier
920
An 850 mW X-Band SiGe power amplifier
921
An 850 nm dielectric guide VCSEL for data communication links
922
An 850 nm wavelength monolithic integrated photoreceiver with a single-power-supplied transimpedance amplifier based on GaAs PHEMT technology
923
An 850-nm InAlGaAs strained quantum-well vertical-cavity surface-emitting laser grown on GaAs (311)B substrate with high-polarization stability
924
An 850-nm Normal-Incidence Germanium Metal–Semiconductor–Metal Photodetector With 13-GHz Bandwidth and 8-
A Dark Current
925
An 85-116 GHz SIS receiver using inductively shunted edge junctions
926
An 852×600 pixel OLED-on-silicon color microdisplay using CMOS subthreshold-voltage-scaling current drivers
927
An 852/spl times/600 pixel OLED-on-silicon color microdisplay chip using CMOS sub-threshold-voltage-scaling current driver
928
An 852x600 pixel OLED-on-silicon color microdisplay chip using CMOS sub-threshold-voltage-scaling current driver
929
An 85-95.2 GHz transformer-based injection-locked frequency tripler in 65nm CMOS
930
An 85dB dynamic range transimpedance amplifier in 40nm CMOS technology
931
An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration
932
An 85-GHz injection-locked frequency divider with current-reuse pre-amplifier technique
933
An 85-MHz fourth-order programmable IIR digital filter chip
934
An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting
935
An 85mW 14-bit 150MS/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS
936
An 85mW 14-bit 150MS/s pipelined ADC with a merged first and second MDAC
937
An 85ns 1Mb DRAM in a plastic DIP
938
An 85-W Multi-Octave Push–Pull GaN HEMT Power Amplifier for High-Efficiency Communication Applications at Microwave Frequencies
939
An 85-watt dissipation silicon power transistor
940
An 85-watt dissipation silicon power transistor
941
An 85-watt dissipation silicon power transistor
942
An 86 K component bipolar VLSI masterslice with a 290-ps loaded gate delay
943
An 86 mW 98GOPS ANN-Searching Processor for Full-HD 30 fps Video Object Recognition With Zeroless Locality-Sensitive Hashing
944
An 86% Efficiency 12 µW Self-Sustaining PV Energy Harvesting System With Hysteresis Regulation and Time-Domain MPPT for IOT Smart Nodes
945
An 86–92 GHz Frequency Shift Keying Transmitter With an Integrated Antenna in 0.5
E/D-PHEMT Technology
946
An 860 to 960MHz RFID Reader IC in CMOS
947
An 860-Mb/s (8158,7136) Low-Density Parity-Check Encoder
948
An 86-106 GHz quasi-integrated low noise Schottky receiver
949
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler
950
An 865-μW H.264/AVC Video Decoder for Mobile Applications
951
An 87 pico-second cmos variable delay line incorporating the parallel-resonator loads in K-band
952
An 87×49 mutual capacitance touch sensing IC enabling 0.5 mm-diameter stylus signal detection at 240 Hz-reporting-rate with palm rejection
953
An 87-
Iontophoresis Controller IC With Dual-Mode Impedance Sensor for Patch-Type Transdermal Drug Delivery System
954
An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS
955
An 87mA·min iontophoresis controller IC with dual-mode impedance sensor for patch-type transdermal drug delivery system
956
An 88 fs fiber soliton laser at 1.56 µm using a quantum well saturable absorber with an ultrafast intersubband transition
957
An 88%-Power-Efficiency Accuracy-Enhanced DC-DC Conversion System for Transcutaneous-Powered Cochlear Implants
958
An 880 / 1760 MHz tunable bandwidth active RC low-pass filter using high gain amplifier
959
An 880 MHz ladder filter formed by arrays of laterally vibrating thin film Lithium Niobate resonators
960
An 88dB 48 KHz full feed-forward sigma-delta modulator
961
An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers
962
An 88dB SNR, 30µm pixel pitch Infra-Red image sensor with a 2-step 16 bit A/D conversion
963
An 88-way multiprocessor within an FPGA with customizable instructions
964
An 89 GHz single-balanced mixer design in 1 um InP DHBT technology
965
An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips
966
An 89dB low-power CMOS ΣΔ modulator for Bluetooth application
967
An 8Ã\x973.2Gb/s Parallel Receiver with Collaborative Timing Recovery
968
An 8Ã\x978 IEEE-Compliant Lifting-Based Multiplierless IDCT Structure and Algorithm
969
An 8Ã\x978 Switch Matrix MMIC Integrating Eight InP-HEMT SP8T Switches for 10-Gbit/s Systems
970
An 8-approximation algorithm for the subset feedback vertex set problem
971
An 8-b 1.3-MHz successive-approximation A/D converter
972
An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC
973
An 8b 100mhz Folding Adc
974
An 8b 100MS/s flash ADC
975
An 8-b 100-MSample/s CMOS pipelined folding ADC
976
An 8b 125Msamples/s 71mW A/D converter with 1.8 v power supply
977
An 8b 150 MSample/s serial ADC
978
An 8-b 1-GSmaples/s CMOS Cascaded Folding and Interpolating ADC
979
An 8b 20mhz Cmos Half-Flash A/D Converter
980
An 8-b 20-Msample/s pipelined A/D converter in 0.5-/spl mu/m CMOS with 7.8 ENOB
981
An 8b 220 MS/s 0.25 μm CMOS pipeline ADC with on-chip RC-filter based voltage references
982
An 8b 240 MS/s 1.36 mm
2
104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs
983
An 8b 250MHz A/D converter
984
An 8-b 250-Msample/s power optimized pipelined A/D converter in 0.18-µm CMOS
985
An 8b 350MHz flash ADC
986
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
987
An 8b 500MHz ADC
988
An 8-b 50-MHz 225-mW submicron CMOS ADC using saturation eliminated comparators
989
An 8b 50MHz video ADC with folding and interpolation techniques
990
An 8b 50ns monolithic A/D converter with internal S/H
991
An 8b 600MHz flash A/D converter with multistage duplex gray coding
992
An 8b 600MS/s 200mW CMOS folding A/D converter using an amplifier preset technique
993
An 8-b 600MSmaples/s folding and interpolating ADC
994
An 8-b 650-MHz folding ADC
995
An 8-b 800-MHz DAC
996
An 8b 80MSample/s pipelined ADC with background calibration
997
An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS
998
An 8b ADC with over-Nyquist input at 300 Msps conversion rate
999
An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate
1000
An 8-b cascaded folding A/D converter with a new fully differential source follower
Control Strategy for Switching Converters in Sliding-Mode Current Control
-band ferrite coaxial line modulator
algorithm for partial fraction expansion
norm bound for state variables in second-order recursive digital filter
