ليست عنوان مقالات لاتين فني مهندسي Hardware accelerating audio coding algorithms Hardware implementation of fingerprint image thinning algorithm in FPGA device

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1

Hardware accelerating audio coding algorithms

2

HARDWARE ACCELERATION ALONE WILL NOT MAKE FAULT GRADING ULSI A REALITY

3

Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism

4

Hardware acceleration architecture for EtherCAT master controller

5

Hardware Acceleration for 3D Image Reconstruction

6

Hardware Acceleration for 3-D Radiation Dose Calculation

7

Hardware Acceleration for Conditional State-Based Communication Scheduling on Real-Time Ethernet

8

Hardware Acceleration for Constraint Solving for Random Simulation

9

Hardware Acceleration for Finite Element Electromagnetics: Efficient Sparse Matrix Floating-Point Computations with Field Programmable Gate Arrays

10

Hardware Acceleration for Finite-Element Electromagnetics: Efficient Sparse Matrix Floating-Point Computations With FPGAs

11

Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systems

12

Hardware Acceleration for Media/Transaction Applications in Network Processors

13

Hardware acceleration for motion tracking system used in image-guided surgery

14

Hardware acceleration for neuromorphic computing: An evolving view

15

Hardware acceleration for programs in SSA form

16

Hardware acceleration for rapid prototyping of communication system

17

Hardware Acceleration for Real Time Simulation of Physiological Systems

18

Hardware acceleration for similarity computations of feature vectors

19

Hardware acceleration for similarity measurement in natural language processing

20

Hardware acceleration for sparse fourier image reconstruction

21

Hardware acceleration for the banded Smith-Waterman algorithm with the cycled systolic array

22

Hardware acceleration for tracking by computing low-order geometric moments

23

Hardware acceleration for verifiable, adaptive real-time communication

24

Hardware Acceleration in Ceph Distributed File System

25

Hardware acceleration in computer networks

26

Hardware acceleration of a face detection system on FPGA

27

Hardware acceleration of approximate palindromes searching

28

Hardware Acceleration of Approximate Tandem Repeat Detection

29

Hardware Acceleration of Background Modeling in the Compressed Domain

30

Hardware Acceleration of Barrier Communication for Large Scale Parallel Computer

31

Hardware acceleration of biomedical models with OpenCMISS and CellML

32

Hardware Acceleration of BLOB Detection for Image Processing

33

Hardware acceleration of combined cipher and forward error correction for low-power wireless applications

34

Hardware acceleration of deadlock avoidance and detection in real-time operating systems

35

Hardware acceleration of divide-and-conquer paradigms: a case study

36

Hardware acceleration of FDTD computations for 3-D microwave breast tomography

37

Hardware Acceleration of Gate Array Layout

38

Hardware acceleration of Hadoop MapReduce

39

Hardware acceleration of hidden Markov model decoding for person detection

40

Hardware acceleration of iterative image reconstruction for X-ray computed tomography

41

Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA

42

Hardware acceleration of multi-view face detection

43

Hardware acceleration of MUSIC based DoA estimator in MUBTS

44

Hardware Acceleration of Online Error Detection in Many-Core Processors

45

Hardware Acceleration of OpenSSL Cryptographic Functions for High-Performance Internet Security

46

Hardware acceleration of Private Information Retrieval protocols using GPUs

47

Hardware acceleration of pseudo-random number generation for simulation applications

48

Hardware acceleration of regular expression repetitions in deep packet inspection

49

Hardware acceleration of Scatter Search

50

Hardware acceleration of sequence alignment algorithms-an overview

51

Hardware Acceleration of Short Read Mapping

52

Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins

53

Hardware acceleration of SVM-based traffic classification on FPGA

54

Hardware acceleration of the 3D finite-difference time-domain method

55

Hardware acceleration of the Integer Karhunen-Loève Transform algorithm for satellite image compression

56

Hardware acceleration of the robust header compression (RoHC) algorithm

57

Hardware acceleration on HPRC of a CNN-based algorithm for astronomical images reduction

58

Hardware acceleration prospects and challenges for high performance computing

59

Hardware acceleration with pipelined adder for Support Vector Machine classifier

60

Hardware accelerator design for data centers

61

Hardware accelerator design for video segmentation with multi-modal background modelling

62

Hardware accelerator for 3D method of moments based parasitic extraction

63

Hardware accelerator for biological protein sequence alignment on reconfigurable Networks-on-Chip

64

Hardware Accelerator for BLAST

65

Hardware Accelerator for Dictionary-Based Compression of MMP Algorithm

66

Hardware accelerator for fast image/video thinning

67

Hardware Accelerator for Full-Text Search (HAFTS) with Succinct Data Structure

68

Hardware Accelerator for Generating Primitive Polynomials over GF(3)

69

Hardware Accelerator for Genomic Sequence Alignment

70

Hardware accelerator for low-power sensor hub MCU to process sensor fusion algorithm

71

Hardware accelerator for minimum mean square error interference alignment

72

Hardware Accelerator for Prediction of Exons

73

Hardware accelerator for real-time image resizing

74

Hardware accelerator for self adaptive augmented reality systems

75

Hardware accelerator for similarity based data dedupe

76

Hardware accelerator for subgraph isomorphism problems

77

Hardware accelerator implementation on FPGA for video processing

78

Hardware accelerator IP-core for wireless 802.16 MAC

79

Hardware accelerators for biocomputing: A survey

80

Hardware accelerators for CAD

81

Hardware accelerators for CAD

82

Hardware Accelerators for Evolving Building Block Modules for Artificial Brains

83

Hardware accelerators for information retrieval and data mining

84

Hardware accelerators for pairing based cryptosystems

85

Hardware accelerators for STABLE-H

86

Hardware accelerators for timing simulation of VLSI digital circuits

87

Hardware Accelerators in Computational Biology: Application, Potential, and Challenges

88

Hardware Accelerators in the Design Automation Environment

89

Hardware accelerators-meeting the RISC challenge

90

Hardware active axon model simulating chaotic phenomena

91

Hardware adaptation for multimedia application case study: Augmented reality

92

Hardware aging-based software metering

93

Hardware Agnostic Approach to TPS Life Cycle Sustainment

94

Hardware algorithm for variable precision multiplication on FPGA

95

Hardware algorithms for determining similarity between two strings

96

Hardware Algorithms for Nonnumeric Computation

97

Hardware Algorithms for Polygon Matching

98

Hardware allocation in FIDIAS system

99

Hardware amount evaluation of the improved WEP on an FPGA

100

Hardware analysis of decoding algorithms for AGC

101

Hardware and a software architecture for monitoring of micro stepping motors

102

Hardware and algorithms for the functional evaluation of cellular neural networks and analog arrays

103

Hardware and algorithms for ultrasonic depth imaging

104

Hardware and applications of AsAP: An asynchronous array of simple processors

105

Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow

106

Hardware and compiler-directed cache coherence in large-scale multiprocessors: Design considerations and performance study

107

Hardware and Control Implementation of Electric Springs for Stabilizing Future Smart Grid With Intermittent Renewable Energy Sources

108

Hardware and operating system support for conservative garbage collection

109

Hardware and Physical Layer Adaptation for a Power Constrained MIMO OFDM System

110

Hardware and process dependence of electron shading damage in a high density plasma oxide etch tool

111

Hardware and Signal Processing for a Novel Multi-Lap-Joint Measurement System for Automated Welding Applications

112

Hardware and simulation study of MPPT charge controller for non-conventinal energy sources

113

Hardware and software architecture for AUV based on low-cost sensors

114

Hardware and software architecture for execution control of an autonomous mobile robot

115

Hardware and software architecture for intelligent robot control-an approach to dual control architecture

116

Hardware and Software Architecture for Nonlinear Control of Multirotor Helicopters

117

Hardware and software architecture for overhead line rating monitoring

118

Hardware and software architecture of a bimanual mobile manipulator for industrial application

119

Hardware and software architecture of a mobile robot with anthropomorphic arm

120

Hardware and software architecture of a smart meter based on electrical signature analysis

121

Hardware and software architecture of ABBY: An industrial mobile manipulator

122

Hardware and software architecture of the bimanual mobile manipulation robot HoLLiE and its actuated upper body

123

Hardware and software architectures for realizing a knowledge based system on eave

124

Hardware and software architectures for the CELL processor

125

Hardware and software as dual languages for computer system modeling

126

Hardware and Software Aspects of Computer-Controlled TV

127

Hardware and software aspects of power system simulation, developments at the University of Bath

128

Hardware and Software Aspects of the Design and Assembly of a New Humanoid Robot for RoboCup Soccer

129

Hardware and software cache prefetching techniques for MPEG benchmarks

130

Hardware and Software Co-design for Robot Arm Position Control Using VHDL and FPGA

131

Hardware and software co-design for robust and resilient execution

132

Hardware and software co-design for the AAC audio decoder

133

Hardware and software co-design in space compaction of cores-based digital circuits

134

Hardware and Software Co-design of the Moving Object Tracking System

135

Hardware and software compatibility issues [computers in education]

136

Hardware and software complex configuration for automated wildfire detection

137

Hardware and Software Complex for MM-Wave Spectroscopic Research

138

Hardware and software complex for the investigations of digital-analog follow-up motor

139

Hardware and software consideration to use near real time MSG-SEVIRI and NOAA-AVHRR images

140

Hardware and software considerations for active noise control

141

Hardware and software considerations for implementing hardware-in-the loop traffic simulation

142

Hardware and software considerations for UAS

143

Hardware and software considerations for unmanned aircraft systems

144

Hardware and Software Design between Microcontroller and Computer Based on USB Interface

145

Hardware and software design for QR Decomposition Recursive Least Square algorithm

146

Hardware and software design of a low DC-link voltage and wide compensation range thyristor controlled LC-coupling hybrid active power filter

147

Hardware and software design of an automated testing tool for traffic controllers

148

Hardware and software design of digital hearing aids based on fixed microphone array

149

Hardware and software development and integration in an FPGA embedded processor based control system module for the ALS

150

Hardware and software development of an intelligent pneutronic robot

151

Hardware and software effective configurations for multi-input fuzzy logic controllers

152

Hardware and software effective configurations for multi-input fuzzy logic controllers

153

Hardware and software fault simulation

154

Hardware and software fault tolerance using fail-silent virtual duplex systems

155

Hardware and software fault tolerance: a unified architectural approach

156

Hardware and software for utilizing manipulators as accessible tools

157

Hardware and software front-end based on the USRP for experimental X-band Synthetic Aperture Radar

158

Hardware and software implementation for an auto-calibrated measurement system

159

Hardware and software implementation for traffic control using distributed processing

160

Hardware and software implementation of a travelling wave based protection relay

161

Hardware and software implementation of sensorless rotor temperature estimation technique for Permanent Magnet Synchronous Motor

162

Hardware and software implementations of an MMSE equalizer for MIMO-OFDM based WLAN

163

Hardware and software implications of creating Bluetooth scatternet devices

164

Hardware and software implications of representing scenes as data

165

Hardware and Software Improvements for VBNA Calibration

166

Hardware and software in a nontechnical environment

167

Hardware and software infrastructure for a family of floating-gate based FPAAs

168

Hardware and software instrumentation continually contribute to quality

169

Hardware and software integrated toolkit for low cost analog fuzzy controllers

170

Hardware and software integration for domestic stairs cleaning robot

171

Hardware and software integration to support real-time space-link emulation

172

Hardware and Software Interface of a Spectrophotometer System to a PDP-11 Digital Computer

173

Hardware and software methods applied for high-speed digital receivers design

174

Hardware and software normal basis arithmetic for pairing-based cryptography in characteristic three

175

Hardware and software paths toward further integration of European power systems

176

Hardware and software performance assessment of a multilevel inverter control

177

Hardware and software performance of image processing applications on reconfigurable systems

178

Hardware and software platform for real-time processing and visualization of echographic radiofrequency signals

179

Hardware and software prototyping for application-specific real-time systems

180

Hardware and software readiness: A systems approach

181

Hardware and Software Realization of EDSD for Acupuncture Research and Practice

182

Hardware and software realization of time error measurements with real-time assessment of ADEV, TDEV, and MTIE

183

Hardware And Software Requirements For A Transmission System Harmonic Measurement System

184

Hardware and software requirements for implementing a high-performance superconductivity circuits-based accelerator

185

Hardware and software simulation of transient pulse impact on integrated circuits

186

Hardware and software solutions for a conventional electric-powered wheelchair

187

Hardware and software solutions for wireless mesh network testbeds

188

Hardware and Software Stack for an SDR-Based RFID Test Platform

189

Hardware and Software Support for NUMA Computing on Configurable Emulated Shared Memory Architectures

190

Hardware and software support for the implementation of dipolar system simulations onto an accelerator

191

Hardware and software symbiosis helps smart card evolution

192

Hardware and software synthesis of image filters from CAL dataflow specification

193

Hardware and software system acoustic control environmentally hazardous objects

194

Hardware and software techniques for controlling DRAM power modes

195

Hardware and software techniques for power conservation in portable devices

196

Hardware and software to design continuous data logger used in marine controllable pitch propeller operation

197

Hardware and software tools and laboratory experiments for an undergraduate EET course in digital signal processing

198

Hardware and software tools for motion control of mobile robotic system

199

Hardware and software tracking for smart pen interface in wearable computing and mixed reality

200

Hardware and software upgrades for the saturn data acquisition triggers and time base (work supported by the Dept. of Energy)

201

Hardware- and software-based collective communication on the Quadrics network

202

Hardware and software-in-the-loop techniques using the OPNET modeling tool for JTRS developmental testing

203

Hardware annealing for fast retrieval of optimal solutions in Hopfield neural networks

204

Hardware annealing in electronic neural networks

205

Hardware annealing on DT-CNN using CAM²

206

Hardware approach to automatic testing

207

Hardware approaches to cache coherence in shared-memory multiprocessors, Part 1

208

Hardware approaches to cache coherence in shared-memory multiprocessors. 2

209

Hardware Approaches to Practice of "in vivo" Bioimpedance Measurement in Various Noise Environment Conditions, in Treatment-and-Prophylactic Institutions

210

Hardware approaches to vector plane rotation

211

Hardware architecture and FPGA implementation of a parallel elitism-based compact genetic algorihm

212

Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local features

213

Hardware architecture and trade-offs for generic inversion of one-way functions

214

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

215

Hardware Architecture Considerations in the WE32100 Chip Set

216

Hardware architecture dedicated for arithmetic mean filtration implemented in FPGA

217

Hardware architecture design and implementation for FMCW radar signal processing algorithm

218

Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies

219

Hardware architecture design and mapping of ‘Fast Inverse Square Root’ algorithm

220

Hardware architecture design for explicit model predictive control

221

Hardware architecture design for H.264/AVC intra frame coder

222

Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264

223

Hardware architecture design for vehicle detection using a stereo camera

224

Hardware architecture design for visual processing: present and future

225

Hardware architecture design of an H.264/AVC video codec

226

Hardware architecture design of Anemia detecting regression model based on FPGA

227

Hardware Architecture Design of CABAC Codec for H.264/AVC

228

Hardware architecture design of face recognition system based on FPGA

229

Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation

230

Hardware architecture design of hybrid distributed video coding with frame level coding mode selection

231

Hardware Architecture Design of Image Preprocessing and Phase Calculating Algorithms Based on FPGA

232

Hardware architecture design of video compression for multimedia communication systems

233

Hardware Architecture Exploration of IEEE 802.11n Receiver Using SystemC Transaction Level Modeling

234

Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory

235

Hardware architecture for a modular autonomous underwater vehicle STARFISH

236

Hardware architecture for accelerating communication on Maestro3 cluster network

237

Hardware architecture for advanced image processing

238

Hardware architecture for AVS entropy encoder

239

Hardware architecture for data concealment using sub-band coding, LSB coding and pseudo-random bit stream generators

240

Hardware architecture for data concealment using sub-band coding, LSB coding and pseudo-random bit stream generators

241

Hardware architecture for detecting laser point using FPGA

242

Hardware Architecture for Exponentiation Based on Square Root Extraction over GF(2m)

243

Hardware architecture for fast Intra mode and direction prediction in real-time MPEG-2 to H.264/AVC transcoder

244

Hardware architecture for finding shortest paths

245

Hardware Architecture for FPGA Implementation of a Neural Network and Its Application in Images Processing

246

Hardware Architecture for FPGA Implemetation of Neural Network and its Application in Images Processing

247

Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile

248

Hardware architecture for H.264/AVC deblocking filter algorithm

249

Hardware architecture for H.264/AVC INTRA 16×16 frame processing

250

Hardware architecture for H.264/AVC intra 16×16 frame processing

251

Hardware architecture for hierarchical control of large Petri net

252

Hardware architecture for high-accuracy real-time pedestrian detection with CoHOG features

253

Hardware Architecture for High-Performance Regular Expression Matching

254

Hardware architecture for high-speed real-time dynamic programming applications

255

Hardware Architecture for HOG Feature Extraction

256

Hardware architecture for Java in a hardware/software co-design of the virtual machine

257

Hardware architecture for Kohonen network

258

Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

259

Hardware architecture for list successive cancellation polar decoder

260

Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding

261

Hardware architecture for nanorobot application in cerebral aneurysm

262

Hardware architecture for on-chip unsupervised online neural spike sorting

263

Hardware architecture for optical flow estimation in real time

264

Hardware architecture for optical packet and burst switching applications

265

Hardware architecture for packet classification with prefix coloring

266

Hardware Architecture for Particle Swarm Optimization Using Floating-Point Arithmetic

267

Hardware architecture for real time H.264 CABAC decoding for HDTV applications

268

Hardware architecture for real-time distance transform

269

Hardware architecture for real-time HD(1920×1080@60fps) H.264/AVC intra prediction

270

Hardware architecture for real-time satellite SAR processing

271

Hardware architecture for the fast pattern matching

272

Hardware architecture for the TROPICO-RA switching system

273

Hardware architecture for transputer-based embedded control

274

Hardware Architecture for Video Authentication Using Sensor Pattern Noise

275

Hardware architecture modelling using an object-oriented method

276

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method

277

Hardware architecture of a neural net based retina implant for patients suffering from retinitis pigmentosa

278

Hardware Architecture of a Parallel Pattern Matching Engine

279

Hardware architecture of a unified embedded engineering learning platform

280

Hardware architecture of an Internet Protocol Version 6 processor

281

Hardware architecture of an SVD based MIMO OFDM channel estimator

282

Hardware architecture of bi-cubic convolution interpolation for real-time image scaling

283

Hardware Architecture of Improved Tomlinson-Harashima Precoding for Downlink MC-CDMA

284

Hardware Architecture of IOTA Pulse Shaping Filters for Multicarrier Systems

285

Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA

286

Hardware Architecture of Protection Switching Device (PSD)

287

Hardware Architecture of the EKF Prediction Stage applied to mobile robot localization

288

Hardware architecture of the fast mode decision algorithm for H.265/HEVC

289

Hardware architecture of time domain LTE baseband signal processor

290

Hardware Architecture Optimized for Iris Recognition

291

Hardware architecture specification and constraint-based WCET computation

292

Hardware Architecture Study for NASA´s Space Software Defined Radios

293

Hardware architecture to locate multiple objects in video images

294

Hardware Architecture to Realize Multi-layer Image Processing in Real-time

295

Hardware architectures

296

Hardware Architectures for Adaptive Background Modelling

297

Hardware architectures for eigenvalue computation of real symmetric matrices

298

Hardware architectures for inversion in GF(2^m) using polynomial and gaussian normal basis

299

Hardware architectures for lattice decoders

300

Hardware architectures for Monte-Carlo based financial simulations

301

Hardware architectures for successive cancellation decoding of polar codes

302

Hardware Architectures for the Generalized Finite Automata Algorithm

303

Hardware architectures for the H.265/HEVC discrete cosine transform

304

Hardware architectures of adaptive equalizers for the HDTV receiver

305

Hardware architectures proposed for cryptosystems based on hyperelliptic curves

306

Hardware as a Service (HaaS): Physical and virtual hardware on demand

307

Hardware as a Service (HaaS): The completion of the cloud stack

308

Hardware aspects of a real-time software clock

309

Hardware aspects of fixed relay station design for OFDM(A) based wireless relay networks

310

Hardware assist for distributed shared memory

311

Hardware Assistance for Z-Buffer Visible Surface Algorithms

312

Hardware Assisted Address Monitoring System

313

Hardware Assisted Clock Synchronization for Real-Time Sensor Networks

314

Hardware assisted COTS IEEE 1588 solution for x86 Linux and its performance evaluation

315

Hardware assisted multichannel volume rendering

316

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

317

Hardware Assisted Pruned Index System For Consumer Electronics

318

Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec

319

Hardware assisted real-time rollback in the advanced fault-tolerant data processor

320

Hardware assisted recovery from transient errors in redundant processing systems

321

Hardware assisted resource sharing platform for personal cloud

322

Hardware assisted thread assignment for RISC based MPSoCs in invasive computing

323

Hardware assisted two dimensional ultra fast placement

324

Hardware assisted volume rendering of unstructured grids by incremental slicing

325

Hardware asynchronous cellular automata of spiking neural networks on SoC for autonomous machines

326

Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation

327

Hardware attack risk assessment

328

Hardware authentication based on PUFs and SHA-3 2^nd round candidates

329

Hardware authentication leveraging performance limits in detailed simulations and emulations

330

Hardware autonomy and space systems

331

Hardware Aware eIRA LDPC Code Generation

332

Hardware Aware Optimization of an Ultra Low Power UWB Communication System

333

Hardware based algorithm for conflict diagnosis in SAT solver

334

Hardware based analysis of RFID anti-collision protocols based on the standard EPCglobal Class-1 Generation-2

335

Hardware based comparison of buck-boost converter topologies in MPPT systems

336

Hardware based design and performance evaluation of a tree based RFID anti-collision protocol

337

Hardware based encryption for wireless networks

338

Hardware based error and flow control in the Axon gigabit host-network interface

339

Hardware based frequency/voltage control of voltage frequency island systems

340

Hardware Based Fuzzy Logic Controllers Using Frequency Domain Singleton Fuzzification

341

Hardware Based I/O Virtualization Technologies for Hypervisors, Configurations and Advantages - A Study

342

Hardware based neural network data fusion for classification of Earth surface conditions

343

Hardware Based Online Profiling in AMIDAR Processors

344

Hardware based pattern matching technique for packet inspection of high speed network

345

Hardware based performance analysis of a multi-function single-phase PV-AF system

346

Hardware based projection onto the parity polytope and probability simplex

347

Hardware based realtime, fast and highly secured speech communication using FPGA

348

Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

349

Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

350

Hardware block for use in programmable microwave function arrays

351

Hardware bottleneck evaluation and analysis of a software PC-based router

352

Hardware Building Blocks for High Data-Rate Fault-Tolerant In-vehicle Networking

353

Hardware building blocks of a hierarchical battery management system for a fuel cell HEV

354

Hardware calibration of the modulated wideband converter

355

Hardware cancellation of the direct coupling in a stepped CW ground penetrating radar

356

Hardware Capacity Evaluation in Shared-Nothing Data Warehouses

357

Hardware centric automatic recognition of road signs

358

Hardware challenges and their resolution in advancing WirelessHART

359

Hardware channel model for ultra wideband systems

360

Hardware check of arithmetic devices with abridged execution of operations

361

Hardware checker module

362

Hardware circuit design of copying manufacturing oriented complete software type CNC system

363

Hardware circuit design of NC system based on ARM and FPGA

364

Hardware Circuit Design on Torsional Spring Testing

365

Hardware close programming for freshmen

366

Hardware code generation from dataflow programs

367

Hardware combinatorial optimization problems solver by hysteresis neural networks

368

Hardware comparison capturing received signal strength indication (RSSI) for wireless sensors network (WSN)

369

Hardware Comparison of the Hash Function Candidates RADIOGATÃ\x9aN, MAME, and LAKE

370

Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers

371

Hardware compatibility issues in the PC card power interface

372

Hardware competitions in engineering education

373

Hardware compilation for FPGA-based configurable computing machines

374

Hardware compilation for FPGAs: imperative and declarative approaches for a robotics interface

375

Hardware compilation for software engineers: an ATM example

376

Hardware Compilation from an RTL to a Storage Logic Array Target

377

Hardware Compilation from Machine Code with M2V

378

Hardware compilation of application-specific memory-access interconnect

379

Hardware compilation technology for embedded image processing

380

Hardware compilation: translating programs into circuits

381

Hardware compiler realising concurrent processes in reconfigurable logic

382

Hardware complexities of algebraic soft-decision Reed-Solomon decoders and comparisons

383

Hardware complexities of low-complexity Chase Reed Solomon decoders and comparisons

384

Hardware complexity and parallel computation

385

Hardware complexity metrics for high level synthesis of software functions

386

Hardware complexity of a correlation based background DAC error estimation technique for sigma-delta ADCs

387

Hardware complexity of binary distributed detection systems with isolated local Bayesian detectors

388

Hardware Complexity of Modular Multiplication and Exponentiation

389

Hardware complexity of SHA-1 and SHA-256 based on area and time analysis

390

Hardware compliant approximate image codes

391

Hardware composition with hardware flowcharts and process algebras

392

Hardware compressed main memory: operating system support and performance evaluation

393

Hardware compression solution based on HWT for low power image transmission in WSN

394

Hardware compression speeds on bitmap fail display

395

Hardware Computation of Moment Functions in a Silicon Retina using Binary Patterns

396

Hardware Computation of the PageRank Eigenvector

397

Hardware computing for brain network analysis

398

Hardware concurrent garbage collection for short-lived objects in an object-oriented processor

399

Hardware conditioning in process of high speed imaging

400

Hardware configuration for effective control of elliptic-based low-pass wave-digital filters

401

Hardware configuration of hexapod robot to force feedback control development

402

Hardware considerations and design of IIR filters for real-time filtering of TV signals

403

Hardware Considerations for Digital Audio Broadcasting System

404

Hardware Considerations for Spectral Encoded UWB Transmitters

405

Hardware considerations in FFT processors

406

Hardware Considerations of a Spatial Filter for Decorrelating High-density Multielectrode Neural Recordings

407

Hardware Constrained LEO Satellite DS Signal Partial-Band Parallel Acquisition Method

408

Hardware construction of a 5 kW inverter for AC power supply applications

409

Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems

410

Hardware control of a real-time multichannel digital signal processing system

411

Hardware control of an active magnetic shield

412

Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture

413

Hardware controller using reconfigurable logic for a “ball and beam” mock-up

414

Hardware controls for the STAR experiment at RHIC

415

Hardware controls for the STAR experiment at RHIC

416

Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC

417

Hardware Coprocessor Design for Fingerprint Image Enhancement

418

Hardware Coprocessor Synthesis from an ANSI C Specification

419

Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding

420

Hardware Correlation of Ultra-Wideband RF Signals Generated via Optical Pulse Shaping

421

Hardware Co-simulation for Chroma-Keying in Real Time

422

Hardware co-simulation of Walsh sequences for 3G Software Defined Radio

423

Hardware Cost Analysis for Weakly Programmable Processor Arrays

424

Hardware cost and capacity analysis of future TDM- and WDM-PON access networks

425

Hardware cost estimation techniques for C-level description

426

Hardware Counters Based Analysis of Memory Accesses in SMPs

427

Hardware course using KUE-CHIP2 boards with FPGAs

428

Hardware cryptography for ubiquitous computing

429

Hardware dead time compensation for VSI based electrical drives

430

Hardware debug - Data overload

431

Hardware debugging method based on signal transitions and transactions

432

Hardware decoding of thalamo-cortical reactions to sensory stimuli through pRAM neural network

433

Hardware Dedicated Integer-Pel Motion Estimator for High Definition H.264/AVC Video Encoder

434

Hardware demonstration of a 2-dimensional wide angle array fed lens

435

Hardware Demonstration of a Home Energy Management System for Demand Response Applications

436

Hardware Demonstration of Extremely Compact Optical True Time Delay Device for Wideband Electronically Steered Antennas

437

Hardware dependency and performance of JavaScript engines used in popular browsers

438

Hardware description language (HDL): An efficient approach to device independent designs for VLSI market segments

439

Hardware description language and information technology of designing data processing and conversion devices

440

Hardware Description Language Applications: An Introdiction and Prognosis

441

Hardware description language based on message passing and implicit pipelining

442

Hardware description language modeling of an electrostatically actuated bi-axial micromirror

443

Hardware description languages for ALECSIS simulator

444

Hardware description languages in Canada

445

Hardware description languages in France

446

Hardware description languages in Great Britain

447

Hardware description languages in Italy

448

Hardware description languages in Japan

449

Hardware Description Languages in Microprogramming Systems

450

Hardware description languages in the Federal Republic of Germany

451

Hardware Description Languages: Voices from the Tower of Babel*

452

Hardware Description Levels and Test for Complex Circuits

453

Hardware design & compression issues in compact Bluetooth enabled wireless telecardiology system

454

Hardware Design and Analysis of Statistical Cipher Feedback Mode Using Serial Transfer

455

Hardware design and arithmetic algorithms for a variable-precision, interval arithmetic coprocessor

456

Hardware design and FPGA implementation for road plane extraction based on V-disparity approach

457

Hardware design and implementation for underwater surface integration

458

Hardware design and implementation of 3780 points FFT based on FPGA in DTTB

459

Hardware design and implementation of a direction of arrival estimation block

460

Hardware design and implementation of a Network-on-Chip based load balancing switch fabric

461

Hardware design and implementation of an Intelligent Haptic Robotic Glove

462

Hardware design and implementation of digital controller for parallel active filters

463

Hardware design and implementation of disparity image post-processing for noise reduction by standard deviation

464

Hardware design and implementation of DOA estimation algorithms for spherical array antennas

465

Hardware Design and Implementation of Intelligent Teaching Aid Based on FDD Theory

466

Hardware design and implementation of MIMO Eigenbeam-space division multiplexing systems for future wireless communications networks

467

Hardware design and implementation of scalar multiplication in elliptic curve cryptography (ECC) over GF(2163) on FPGA

468

Hardware Design and Implementation of SM3 Hash Algorithm for Financial IC Card

469

Hardware design and implementation of Unity Power Factor Rectifiers using microcontrollers

470

Hardware design and implementation of Wi-Fi technology based encryption system

471

Hardware design and performance analysis of VDSL transceivers

472

Hardware Design and Prototype of an Optical Packet-Switched Ring Network Node

473

Hardware design and realization of matrix converter based on DSP & CPLD

474

Hardware Design and System Calibration for Electrical Capacitance Tomography System

475

Hardware design and UKF-based tracking control design of Unmanned Trimaran Surface Vehicle

476

Hardware design and validation of pitching control for micro air vehicles using only pressure information

477

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs

478

Hardware Design and Verification Techniques for Supply Chain Risk Mitigation

479

Hardware design and VLSI implementation of a byte-wise CRC generator chip

480

Hardware Design Automation

481

Hardware design education for short term with high abstraction level of the behavior description language

482

Hardware design for accelerating PNG decode

483

Hardware Design for an IEEE-488/1978 Interface Chip

484

Hardware design for distributed MAS-based fault location in power distribution systems

485

Hardware design for efficient construction of an environment map for mobile robot navigation

486

Hardware design for end-to-end modular exponentiation in redundant number representation

487

Hardware design for fast intermode decision and for residues generaton in a variable block size motion estimation compliant with the H.264/AVC video coding standard

488

Hardware design for MAS power distribution restoration using neural networks

489

Hardware design for modern radar processing

490

Hardware Design for Mpeg-7 Compact Color Descriptor Based on Sub-Block

491

Hardware design for multiplicative modular inverse based on table look up technique

492

Hardware Design for Noise Reduction in Data Acquisition Modules

493

Hardware design for registration of aerial video imagery

494

Hardware design for SHA-1 based on FPGA

495

Hardware design for the 32×32 IDCT of the HEVC video coding standard

496

Hardware design in statement level parallel processing

497

Hardware design issues of fuzzy neural networks

498

Hardware Design Languages for Computer Design and Test

499

Hardware design methodology to synthesize communication interfaces from TLM to RTL

500

Hardware design of 2-D analog filters for directly filtering raster scanned images in real time

501

Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear Pairings

502

Hardware design of a 2-D motion estimation system based on the Hough transform

503

Hardware design of a Binary Integer Decimal-based floating-point adder

504

Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit

505

Hardware design of a body sensor network system used for elder care

506

Hardware design of a color quantization with self-organizing map

507

Hardware design of a fast, parallel Random Tree path planner

508

Hardware design of a full-digital AC-servo driver based on TMS320F2812

509

Hardware Design of a High Performance Multi-Channel High Speed Signal Acquisition and Processing System

510

Hardware design of a Hough transform based 2-D motion estimation system

511

Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding

512

Hardware design of a neural processing unit for bio-inspired computing

513

Hardware design of a reader device in RFID-based class-attendance system

514

Hardware design of a street lighting control system with vehicle and malfunction detection

515

Hardware Design of a Suit of Small Power Frequency-Variable Controlled Equipment

516

Hardware design of a wireless video processing module based on TMS320DM6446

517

Hardware design of ADSP-BF548 based portable patient monitor

518

Hardware design of an eigensolver based on the QR method

519

Hardware Design of an Interface Supporting Both Camera and Display for Mobile Devices

520

Hardware design of an NTT-based polynomial multiplier

521

Hardware Design of Anembedded Real-Time Acoustic Source Location Detector

522

Hardware design of asynchronous fuzzy controllers

523

Hardware Design of Automatic Meter Reading System Based on Internet

524

Hardware Design of Automobile Door with Local Interconnect Network Bus

525

Hardware design of autonomous snake-like robot for reinforcement learning based on environment

526

Hardware design of CMAC neural network for control applications

527

Hardware Design of CP Length Detector for the WirelessMAN-OFDM System

528

Hardware design of CPR Simulation Control System based on SCM

529

Hardware design of data acquisition and processing of digital IF receiver

530

Hardware design of digital AC servo system based on DSP2812

531

Hardware design of ECG data logger

532

Hardware design of embedded fingerprint identification system

533

Hardware Design of Fall Detection System Based on ADXL345 Sensor

534

Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications

535

Hardware Design of Fatigue Detection System Based on PERCLOS

536

Hardware design of features extraction using wavelet packet method for intelligent diagnostic system

537

Hardware design of FFT polynomial multipliers

538

Hardware design of filter bank-based narrowband/wideband interference canceller for overlaid TDMA/CDMA systems

539

Hardware Design of Foundation Fieldbus Intrinsic Safety Communication Protocol Processing Unit

540

Hardware design of gun-borne receiver for the regional positioning system

541

Hardware design of image information processor based on ADSP-TS201 DSPs

542

Hardware design of image recognition system based ARM and FPGA

543

Hardware design of independent experimental platform based on FPGA

544

Hardware design of large-scale sensor-based Electrical Capacitance Tomography systems

545

Hardware design of modular robotic system

546

Hardware design of neural network system state observer

547

Hardware design of one transmission line aeolian vibration monitoring system

548

Hardware design of on-line Jawi character recognition chip using discrete wavelet transform

549

Hardware design of passive acoustic source localization system based on a five-element cross microphone array

550

Hardware design of programmable fuzzy controller on FPGA

551

Hardware Design of Quasi-Cyclic Low-Density Parity-Check Encoder Based on a Novel RC-Scheme

552

Hardware design of real-time offline Jawi character recognition chip using discrete wavelet transform

553

Hardware Design of River Flow Velocity Monitoring System

554

Hardware design of self-organization for clustering

555

Hardware Design of Signal Processing for a Novel Audio Beam Loudspeaker Based on DSP

556

Hardware Design of Signal Processing System Based on DSP

557

Hardware Design of Signal Processing System Based on DSP

558

Hardware Design of Smart Home Energy Management System With Dynamic Price Response

559

Hardware Design of Solid-Liquid Two-Phase Flow Meter

560

Hardware design of spatial mapper for 1.73Gbps multi-user MIMO system of IEEE802.11ac

561

Hardware Design of Sphere Decoding for MIMO Systems

562

Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding

563

Hardware design of the PMSM control system based on DSP and CPLD

564

Hardware design of the scalable video encoder for the multi-source digital home environment

565

Hardware design of the wireless automatic meter reading system based on GPRS

566

Hardware Design of Track Frequency Shift Parameter System

567

Hardware design of vector code correlation method for high-speed template matching

568

Hardware Design of Vehicle Electron Measurement and Experimental Teaching System

569

Hardware Design of Video Compression System in the UAV Based on the ARM Technology

570

Hardware Design of Video Stabilization System Based on TMS320DM642

571

Hardware design on an FPGA chip of impedance force control for interaction between a human operator and a robot arm

572

Hardware design on electric vehicle LCD display system based on CAN bus

573

Hardware design overview of a satellite scatterometer

574

Hardware Design Procedure: Principles and Practices

575

Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness

576

Hardware Designer´s Guide to Fault Attacks

577

Hardware design-for-test process improvements and resulting testability tool requirements

578

Hardware Designing for ABS-S Modulator

579

Hardware Designs for Binary Integer Decimal-Based Rounding

580

Hardware Designs for Decimal Floating-Point Addition and Related Operations

581

Hardware designs for exactly rounded elementary functions

582

Hardware development and application specifications for Li/CoO₂ electrochemical cells

583

Hardware development and implementation of an object tracking algorithm

584

Hardware development and implementation of single phase matrix converter as a cycloconverter and as an inverter

585

Hardware Development And Initial Subassembly Tests Of A Gas-fired Stirling Engine/refrigerant Compressor Assembly

586

Hardware Development and Locomotion Control Strategy for an Over-Ground Gait Trainer: NaTUre-Gaits

587

Hardware development for pervasive healthcare systems: Current status and future directions

588

Hardware development for Smart Meter based innovations

589

Hardware development of the wind tunnel based virtual flight system

590

Hardware development of Voltage Source Inverter for Hybrid Electric Vehicle

591

Hardware Development: Agile and Co-Design

592

Hardware developments for the German SmartSAR program

593

Hardware directed fast eigenface based face detection algorithm using FFT

594

Hardware Discrete Channel Emulator

595

Hardware dissection in computer science as a tool to improve teamwork

596

Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA

597

Hardware EDF scheduler implementation on controller area network controller

598

Hardware Edge Detection using an Altera Stratix NIOS2 Development Kit

599

Hardware efficent viterbi detection for jtter dominant channel

600

Hardware Efficiency Comparison of AES Implementations

601

Hardware efficiency comparison of IP Cores for CAN & LIN protocols

602

Hardware efficiency versus error probability in unreliable computation

603

Hardware efficient AES for image processing with high throughput

604

Hardware Efficient Algorithm for Complex Arithmetic

605

Hardware efficient algorithms for trigonometric functions

606

Hardware efficient approximative matrix inversion for linear pre-coding in massive MIMO

607

Hardware Efficient Architecture for Generating Sine/Cosine Waves

608

Hardware efficient architectures for coupled-form IIR filters

609

Hardware Efficient Architectures for Eigenvalue Computation

610

Hardware efficient architectures of improved Jacobi method to solve the eigen problem

611

Hardware efficient base-4 systolic architecture for computing the discrete Fourier transform

612

Hardware efficient BPSK and QPSK detector

613

Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation

614

Hardware efficient DCT implementation for portable multimedia terminals using subexpression sharing

615

Hardware efficient decoding of LDPC codes using partial-min algorithms

616

Hardware efficient design for narrow band power line communication modem

617

Hardware efficient design of filter banks for video coding

618

Hardware efficient design of speed optimized power stringent Application Specific Processor

619

Hardware efficient design of Variable Length FFT Processor

620

Hardware efficient digital channeliser designs for radar intercept applications

621

Hardware efficient digital filter design by multimode mean field annealing

622

Hardware efficient early termination mechanism in motion estimation for H.264 AVC

623

Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures

624

Hardware efficient fast parallel FIR filter structures based on iterated short convolution

625

Hardware efficient fast parallel FIR filter structures based on iterated short convolution

626

Hardware efficient FIR compensation filter for delta sigma modulator analog to digital converters

627

Hardware efficient FIR filter implementation using subfilters for digital receivers

628

Hardware efficient FIR filter structures from linear program design constraints

629

Hardware efficient fixed-point VLSI architecture for 2D Kurtotic FastICA

630

Hardware efficient FPGA implementation of emotion recognizer for autistic children

631

Hardware efficient frequency estimation and tracking using signal autocorrelations

632

Hardware efficient frequency estimator based on data-aided algorithm for digital video broadcasting system

633

Hardware efficient implementation of video capsule endoscopy

634

Hardware efficient LBIST with complementary weights

635

Hardware efficient learning on a 3-D optoelectronic neural system

636

Hardware efficient logarithmic digital decimation filter

637

Hardware efficient lossless image compression engine

638

Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders

639

Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

640

Hardware efficient narrow band FIR filter

641

Hardware efficient Octaphase-shift keying detector

642

Hardware efficient parallel particle filter for tracking in wireless networks

643

Hardware Efficient Piecewise Linear Branch Predictor

644

Hardware efficient QAM16 all-optical carrier recovery using a single optically-stabilized injection-locked semiconductor laser

645

Hardware Efficient QR Decomposition for GDFE

646

Hardware efficient recursive VLSI architecture for multilevel lifting 2-D DWT

647

Hardware efficient scheme for generating error vector to enhance the performance of secure channel code

648

Hardware Efficient Skip Mode Detection for H.264/AVC

649

Hardware efficient transform designs with cyclic formulation and subexpression sharing

650

Hardware efficient two step iterative matching algorithms for VOQ switches

651

Hardware efficient underwater mine detection and classification

652

Hardware efficient updating technique for LZW CODEC design

653

Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform

654

Hardware efficient, neuromorphic dendritically enhanced readout for liquid state machines

655

Hardware Elliptic Curve Cryptographic Processor Over $\\rm GF(p)$

656

Hardware embedded current control PWM "Hi-PWM" to reduce switching frequency for application to railway

657

Hardware emulation and test at the flightline

658

Hardware emulation board based on FPGAs and programmable interconnections

659

Hardware Emulation Building Blocks for Real-Time Simulation of Large-Scale Power Grids

660

Hardware emulation for functional verification of K5

661

Hardware Emulation for Real-Time Power System Simulation

662

Hardware emulation of a network on chip architecture based on a clockwork routed manhattan street network

663

Hardware emulation of HOG and AMDF based scale and rotation invariant robust shape detection

664

Hardware emulation of multi-level decision feedback equalization

665

Hardware emulation of Quantum Fourier Transform

666

Hardware emulation of transverse flux machines based on an analytical model considering saturation effects

667

Hardware emulation of two-dimensional arrays of detectors

668

Hardware emulation of VLSI designs

669

Hardware emulation of wireless MIMO channel

670

Hardware encoder and decoder for 3-D stereo video streaming applications

671

Hardware engine for real-time pen tracking on electrophoretic displays

672

Hardware Engine for Real-Time Pen Tracking on Electrophoretic Displays

673

Hardware Engine for Supporting Gray-Tone Paintbrush Function on Electrophoretic Papers

674

Hardware engines for bus encryption: a survey of existing techniques

675

Hardware Enhanced Function Allocation Management in Reconfigurable Systems

676

Hardware Equipment for Realtime-Determination of Data Gained from A-Scans by Automatic Ultrasonic Inspection for Flaw-Reconstruction by ALOK

677

Hardware equipment of computer classrooms in Croatian elementary schools

678

Hardware Error Likelihood Induced by the Operation of Software

679

Hardware Estimation and Synthesis for a Codesign System

680

Hardware evaluation of KCM

681

Hardware evaluation of low power communication mechanisms for transport-triggered architectures

682

Hardware evaluation of mathematical functions

683

Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT

684

Hardware evaluation process for tracking edge-lines

685

Hardware event handling in the hardware real-time operating systems

686

Hardware event treating in nMPRA

687

Hardware evolution of analog circuits for in-situ robotic fault-recovery

688

Hardware experiment evaluation of STATCOMs using conventional and direct-current vector control strategies

689

Hardware experiment of nonlinear receding horizon adaptive control

690

Hardware experiments of humanoid robot safe fall using Aldebaran NAO

691

Hardware factorization based on elliptic curve method

692

Hardware fading simulator for a number of narrowband channels with controllable mutual correlation

693

Hardware failure and cost analysis of information technology products

694

Hardware Failure Virtualization Via Software Encoded Processing

695

Hardware Fault Compensation Using Discriminative Learning

696

Hardware Fault Containment In Scalable Shared-memory Multiprocessors

697

Hardware Fault Free Simulation for SOC

698

Hardware fault injection with UMLinux

699

Hardware Fault Tolerance implemented in software at the compiler level with special emphasis on array-variable protection

700

Hardware fault tolerance in arithmetic coding for data compression

701

Hardware fault tolerance: an immunological solution

702

Hardware feasibility analysis for motion segmentation initialization

703

Hardware for a Full Aperture Kicker System for the CPS

704

Hardware for a new fuzzy-based modeling system and its redundancy

705

Hardware for a Wireless Geophysical Monitoring Testbed

706

Hardware for coherent and non-coherent fast acquisition for GPS/GLONASS signals

707

Hardware for computing modular multiplication algorithm

708

Hardware for Detection and Partial Correction of PCM Transmission Errors

709

Hardware for fast global operations on multicomputers

710

Hardware for fast global operations on workstation cluster multicomputers

711

Hardware for high-performance computing: abstract progress, painful consolidation

712

Hardware for image alignment by one shear transformation

713

Hardware for image processing and analysis: The PICAP approach

714

Hardware for image rotation by twice skew transformations

715

Hardware for information processing systems: Today and in the future

716

Hardware for precise in vivo pulse transmit time CNIBP tests

717

Hardware for production test of RFID interface embedded into chips for smart cards and labels used in contactless applications

718

Hardware for rail traffic simulator

719

Hardware for real-time image processing

720

Hardware for seizure prediction: Towards wearable devices to support epileptic people

721

Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors

722

Hardware for speculative run-time parallelization in distributed shared-memory multiprocessors

723

Hardware for two-dimensional digital filtering using Fermat number transforms

724

Hardware for visual image processing

725

Hardware Framework of HAVC System Design

726

Hardware friendly algorithm for the calculation of phase synchronization between neural signals

727

Hardware friendly background analysis based complexity reduction in H.264/AVC multiple reference frames motion estimation

728

Hardware Friendly Mode Decision Algorithm for High Definition AVS Video Encoder

729

Hardware friendly motion estimation algorithm and VLSI architecture for H.264/AVC coding

730

Hardware Friendly Probabilistic Spiking Neural Network With Long-Term and Short-Term Plasticity

731

Hardware friendly schemes to implement exponential linear phase FIR filters

732

Hardware friendly vector quantization algorithm

733

Hardware fuzzy logic kit design

734

Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method

735

Hardware guide winding and hot wire winding

736

Hardware hangover

737

Hardware home energy management system for monitoring the quality of energy service at small consumers

738

Hardware homework as active and experiential learning for first year students in electrical and comtuter engineering

739

Hardware homework for courses in circuits and electronics

740

Hardware hooks for transition scan characterization

741

Hardware ID auto-assigning mechanism for embedded wireless network

742

Hardware identification of cache conflict misses

743

Hardware Impairments Aware Transceiver for Full-Duplex Massive MIMO Relaying

744

Hardware impairments in large-scale MISO systems: Energy efficiency, estimation, and capacity limits

745

Hardware Impairments on LDPC Coded SC-FDE and OFDM in Multi-Gbps WPAN (IEEE 802.15.3c)

746

Hardware implement of numerical control system for bearingless induction motor

747

Hardware Implement of the Forward Value Conversion Algorithm for Delta-Sigma System Based Direct Stream Digital

748

Hardware implementable S-box based on a discretized piecewise linear chaotic map

749

Hardware implementaion of 10w PV panel as STATCOM voltage compensation in a daytime distribution utility

750

Hardware implementation analysis of SHA-3 candidates algorithms

751

Hardware Implementation Analysis of the MD5 Hash Algorithm

752

Hardware implementation and comparison of new defuzzification techniques in fuzzy processors

753

Hardware implementation and control design of generator emulator in multi-converter system

754

Hardware implementation and cost of decoders for digital HDTV

755

Hardware Implementation and cost of Decoders for Digital HDTV

756

Hardware implementation and evaluation of the Flexible router architecture for NoCs

757

Hardware implementation and experiment validation of the VDDRHF color image filter

758

Hardware Implementation and Performance Analysis of a Current-Sensor-Free Single Cell MPPT for High Performance Vehicle Solar Arrays

759

Hardware implementation and power analysis of HWT for medical imaging

760

Hardware implementation and reduction of artifacts from ECG signal

761

Hardware Implementation and Test Results of PEP Chopper Magnet Power Supply System

762

Hardware implementation and testing of effective DPCM image compression technique using multiple-LUT

763

Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique

764

Hardware implementation aspects of a detector based on successive interference cancellation in a DS/CDMA system

765

Hardware implementation aspects of Multi-Step Look-Ahead Σ-Δ modulation-like architectures for all-digital frequency synthesis applications

766

Hardware implementation challenges of modern error control decoders

767

Hardware implementation choices for vehicular telematics systems and simulation results

768

Hardware implementation design of analog neural rank-order filter

769

Hardware implementation design of analog sorting neural network

770

Hardware Implementation for a Genetic Algorithm

771

Hardware implementation for a hand recognition system on FPGA

772

Hardware implementation for a new design of the VBSME Used in H.264/AVC

773

Hardware implementation for calculation of fastest linearly independent spectra over GF(2)

774

Hardware implementation for census 3D disparity map with dynamic search range estimation

775

Hardware implementation for entropy coding and byte stream packing engine in H.264/AVC

776

Hardware implementation for face detection on Xilinx Virtex-II FPGA using the reversible component transformation colour space

777

Hardware implementation for fast convolution with a PN code using field programmable gate array

778

Hardware Implementation for frequent episode discovery in event sequences

779

Hardware implementation for real-time 3D rendering in 2D-to-3D conversion

780

Hardware implementation for receive beamforming and transverse elasticity imaging

781

Hardware implementation for scalable lookahead Regular Expression detection

782

Hardware implementation for sending concealed data in video by using wavelets

783

Hardware implementation for Turbo code-OFDM using Software defined Radio

784

Hardware implementation in DGPS accuracy improvement by using RSCMAC

785

Hardware implementation issues of a BMS decoding approach for AG based codes

786

Hardware implementation issues of carrier synchronization for pilot-symbol assisted bursts: A case study for DVB-RCS2

787

Hardware implementation issues of cascade filters MUD for multirate WCDMA systems

788

Hardware implementation issues of multivariable fuzzy control systems

789

Hardware implementation method for air target recognition and location

790

Hardware implementation of “Supplementary symmetrical logic circuit structure” concepts

791

Hardware Implementation of ${\\rm GF}(2^{m})$ LDPC Decoders

792

Hardware implementation of 128-bit symmetric cipher SEED

793

Hardware implementation of 1D DCT/IDCT for WLAN channel estimation

794

Hardware Implementation of 1D Wavelet Transform on an FPGA for Infrasound Signal Classification

795

Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem

796

Hardware implementation of 4×4 DCT/quantization block using multiplication and error-free algorithm

797

Hardware Implementation of 64B/66B Encoder/Decoder for 10-Gigabit Ethernet

798

Hardware implementation of a `wired-once´ neural net in thin-film technology on a glass substrate

799

Hardware implementation of a 15-channel filter bank

800

Hardware implementation of a 16 kbps subband coder using vector quantization

801

Hardware implementation of a 1D MPI hybrid system for targeted drug delivery

802

Hardware implementation of a 2×2 differential space-time code

803

Hardware implementation of a 2D motion estimation system based on the Hough transform

804

Hardware implementation of a 802.11n MIMO OFDM transceiver

805

Hardware implementation of a background substraction algorithm in FPGA-based platforms

806

Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes

807

Hardware Implementation of a Biometric Fingerprint Identification System with Embedded Matlab

808

Hardware implementation of a biometric recognition algorithm based on in-air signature

809

Hardware Implementation of a Bio-plausible Neuron Model for Evolution and Growth of Spiking Neural Networks on FPGA

810

Hardware Implementation of a Bounded Algorithm for Application of Rules in a Transition P-System

811

Hardware implementation of a broad-band vector spectrum analyzer based on randomized sampling

812

Hardware implementation of a broad-band vector spectrum analyzer based on randomized sampling

813

Hardware implementation of a cascade particle filter

814

Hardware implementation of a centroid-based localization algorithm for mobile sensor networks

815

Hardware implementation of a CNN for analog simulation of reaction-diffusion equations

816

Hardware implementation of a color image decoder for remote database access

817

Hardware implementation of a controller based on neurobiological adaptive models of the human motor-control system

818

Hardware Implementation of a Correlation-based Synchronization Algorithm for Wireless OFDM

819

Hardware implementation of a DCT watermark for CMOS image sensors

820

Hardware implementation of a differential QAM modem

821

Hardware Implementation of a Digital Watermarking System for Video Authentication

822

Hardware Implementation of a Fast and Efficient Haze Removal Method

823

Hardware implementation of a fast FIR filter with residue number system

824

Hardware implementation of a fault recovery protocol compliant with interbus-S standard

825

Hardware implementation of a fingerprinting algorithm suited for digital cinema

826

Hardware Implementation of a Flexible Tag Platform for Passive RFID Devices

827

Hardware implementation of a four-terminal HVDC test-bed

828

Hardware implementation of a FPGA-based universal link for LVDS communications

829

Hardware implementation of a full HD real-time disparity estimation algorithm

830

Hardware implementation of a fuzzy controller for nonlinear application

831

Hardware implementation of a fuzzy guidance system with prescribed waypoint approach trajectory

832

Hardware implementation of a general multi-way jump mechanism

833

Hardware implementation of a high speed floating point multiplier based on FPGA

834

Hardware implementation of a high speed self-synchronizing cipher mode

835

Hardware implementation of a high-performance programmable digital processing system for radar proximity fuze

836

Hardware implementation of a Hilbert transformer

837

Hardware Implementation of a Hybrid Intelligent Controller for a Twin Rotor MIMO

838

Hardware implementation of a hybrid protection scheme for bipolar HVDC line

839

Hardware implementation of a Kullback-Leibler Divergence based signal anomaly detector

840

Hardware implementation of a low power SD card controller

841

Hardware implementation of a low-complexity detector for large MIMO

842

Hardware Implementation of a Mamdani Fuzzy Logic Controller for a Static Compensator in a Multimachine Power System

843

Hardware implementation of a Mamdani fuzzy logic controller for a static compensator in a multimachine power system

844

Hardware implementation of a memory allocator

845

Hardware implementation of a modified randomized cryptographic algorithm

846

Hardware implementation of a Montgomery modular multiplier in a systolic array

847

Hardware implementation of a multiplex wiring system

848

Hardware implementation of a multiprocessor system controlled by Petri nets

849

Hardware implementation of a neural network based path planning algorithm by using the VHDL

850

Hardware implementation of a neural network controller on FPGA for a humanoid robot arm

851

Hardware implementation of a neural network pattern shaper algorithm

852

Hardware Implementation of a Neural-Network Recognition Module for Visual Servoing in a Mobile Robot

853

Hardware implementation of a new adaptive 1D wavelet coding algorithm

854

Hardware implementation of a new ECC key distribution protocol for securing Wireless Sensor Networks

855

Hardware implementation of a new phase measurement algorithm

856

Hardware implementation of a non-coherent IR-UWB receiver synchronization algorithm targeting IEEE 802.15.6 wireless BAN

857

Hardware implementation of a nonlinear processor

858

Hardware implementation of a novel adaptive version of Deflate compression algorithm

859

Hardware implementation of a novel inference engine for interval type-2 fuzzy control on FPGA

860

Hardware implementation of a novel inversion algorithm

861

Hardware implementation of a novel, reduced rating active filter for 3-phase, 4-wire loads

862

Hardware implementation of a Particle Filter for location estimation

863

Hardware implementation of a PCA learning network by an asynchronous PDM digital circuit

864

Hardware implementation of a PIC18F448 based TIM for IEEE1451.2 compliant actuator control

865

Hardware Implementation of a Polyphase Filter Bank for MP3 Decoding

866

Hardware implementation of a practical complexity Spectrally Efficient FDM reconfigurable receiver

867

Hardware implementation of a pulse-stream neural network

868

Hardware Implementation of a RBF Neural Network Controller with a DSP 2812 and an FPGA for Controlling Nonlinear Systems

869

Hardware implementation of a real time neural network controller with a DSP and an FPGA

870

Hardware implementation of a real-time 3D video acquisition system

871

Hardware implementation of a real-time distributed video decoder

872

Hardware implementation of a real-time electromagnetic field analysis system for engineering education

873

Hardware Implementation of a Real-Time Electromagnetic Field Analysis System for Engineering Educational Purposes

874

Hardware implementation of a real-time genetic algorithm for adaptive filtering applications

875

Hardware Implementation of a Real-Time Neural Network Controller Set for Reactive Power Compensation Systems

876

Hardware Implementation of a Real-Time Neural Network Controller With a DSP and an FPGA for Nonlinear Systems

877

Hardware implementation of a real-time operating system

878

Hardware implementation of a recursive digital filter for m.t.i. radar

879

Hardware implementation of a Reed-Solomon soft decoder based on information set decoding

880

Hardware implementation of a robust watermarking technique for digital images

881

Hardware Implementation of a RSS Localization Algorithm for Wireless Capsule Endoscopy

882

Hardware implementation of a secure bridge in Ethernet environments

883

Hardware implementation of a secure random number generator

884

Hardware Implementation of a Ship-Wide Area Differential Protection Scheme

885

Hardware Implementation of a Simple Structure of Addressing Technique for CMAC_GBF

886

Hardware implementation of a single-cycle one-dimensional median filter

887

Hardware implementation of a soft cancellation decoder for polar codes

888

Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array

889

Hardware implementation of a system for highly nonstationary two-dimensional FM signals estimation based on the sliding matrix function

890

Hardware implementation of a systolic antenna array signal processor based on CORDIC arithmetic

891

Hardware implementation of a Test Lab for Smart Home environments

892

Hardware implementation of a three-dimensional finite-difference time-domain algorithm

893

Hardware implementation of a three-phase active filter system with harmonic isolation based on self-tuning-filter

894

Hardware implementation of a universal controller for a GE P50 robot arm

895

Hardware implementation of a VDPCM using parallel processing architecture

896

Hardware implementation of a visual-motion pixel using oriented spatiotemporal neural filters

897

Hardware implementation of a Viterbi decoder using the minimal trellis

898

Hardware implementation of a wavelet based image compression coder

899

Hardware implementation of a wavelet-based radio frequency interference mitigation algorithm for microwave radiometers

900

Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programming

901

Hardware Implementation of Active Contour Algorithm for Fast Cancer Cells Detection

902

Hardware Implementation of ADABOOST ALGORITHM and Verification

903

Hardware Implementation of Adaptive Baemformers Used for Smart Antennas

904

Hardware implementation of adaptive filters

905

Hardware implementation of adaptive motion estimation and compensation for H.264/AVC

906

Hardware implementation of adaptive processing for smart sensor arrays

907

Hardware Implementation of Advanced Encryption Standard

908

Hardware implementation of AI primitives

909

Hardware implementation of all digital calibration for undersampling TIADCs

910

Hardware implementation of an adaptive network-based fuzzy controller for DC-DC converters

911

Hardware implementation of an adaptive network-based fuzzy controller for DC-DC converters

912

Hardware implementation of an Adaptive Noise canceller in an automobile environment

913

Hardware implementation of an additive bit-serial algorithm for the discrete logarithm modulo 2^k

914

Hardware Implementation of an AIS-Based Optimal Excitation Controller for an Electric Ship

915

Hardware Implementation of an AIS-Based Optimal Excitation Controller for an Electric Ship

916

Hardware implementation of an approximate string matching algorithm using bit parallel processing for text information retrieval systems

917

Hardware implementation of an artificial neural network

918

Hardware implementation of an artificial neural network using field programmable gate arrays (FPGA´s)

919

Hardware Implementation of an Automatic Adaptive Centralized Underfrequency Load Shedding Scheme

920

Hardware implementation of an EAN-13 bar code decoder

921

Hardware implementation of an Echo-Canceller for DVB-T On-Channel Repeaters

922

Hardware implementation of an efficient correlator for Golay pairs derived from kernels of lengths 2, 10 and 26

923

Hardware implementation of an elliptic curve processor over GF(p)

924

Hardware implementation of an expandable on-chip learning neural network with 8-neuron and 64-synapse

925

Hardware implementation of an improved fine CFO synchronization for MB-OFDM UWB

926

Hardware implementation of an interference canceller for IDMA wireless communications

927

Hardware implementation of an IR-UWB coordinator node for WBAN applications

928

Hardware implementation of an islanding detection approach based on current and voltage transients

929

Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication

930

Hardware implementation of an omnidirectional camerawith real-time 3D imaging capability

931

Hardware implementation of an on-chip BP learning neural network with programmable neuron characteristics and learning rate adaptation

932

Hardware implementation of an optimized processor architecture for SOBEL image edge detection operator

933

Hardware implementation of an optimized scale-invariant feature detector for robotic applications

934

Hardware implementation of an SAD based stereo vision algorithm

935

Hardware implementation of an SVD based MIMO OFDM channel estimator

936

Hardware implementation of an ultrasonic beamformer

937

Hardware implementation of analog beamformer for phased array radar (PAR)

938

Hardware Implementation of ANFIS Controller for Gas-Particle Separations in Wet Scrubber System

939

Hardware implementation of arithmetic for elliptic curve cryptosystems over GF(2^m)

940

Hardware implementation of ART1 memories using a mixed analog/digital approach

941

Hardware implementation of audio watermarking - covert communication

942

Hardware Implementation of Automated Sensor Self-Validation System for Cupola Furnaces

943

Hardware implementation of backpropagation algorithm based on CHEMFET sensor selectivity

944

Hardware implementation of balance control for three-phase grid connection 5-level Cascaded H-Bridge converter using DSP

945

Hardware implementation of BFNN and RBFNN in FPGA technology: Quantization issues

946

Hardware implementation of block matching algorithm with FPGA technology

947

Hardware implementation of BLTL property checkers for acceleration of statistical model checking

948

Hardware implementation of Bluetooth security

949

Hardware implementation of Boolean neural networks

950

Hardware implementation of boosting based object detection using a high level description

951

Hardware Implementation of Cellular Automata on Systolic Array

952

Hardware implementation of Chinese remainder theorem using redundant binary representation

953

Hardware implementation of CMAC and B-spline neural networks for embedded applications

954

Hardware Implementation of CMAC Neural Network using FPGA Approach

955

Hardware implementation of CMAC neural network with reduced storage requirement

956

Hardware implementation of CNN

957

Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization

958

Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques

959

Hardware implementation of content based video indexing algorithms

960

Hardware implementation of context switching for hard real-time operating systems

961

Hardware Implementation of Continued Logarithm Arithmetic

962

Hardware implementation of convolution using number theoretic transforms

963

Hardware implementation of Cryo-Pneumatic Engine Control Unit

964

Hardware implementation of data compression algorithms for memory energy optimization

965

Hardware implementation of DBNS recoding for ECC processor

966

Hardware implementation of DC-DC converter for MPPT in PV applications

967

Hardware implementation of delay-coded spiking-RBF neural network for unsupervised clustering

968

Hardware Implementation of DES Encryption Cracker

969

Hardware implementation of DES using pipelining concept with time-variable key

970

Hardware implementation of digital beamforming network for Ultra Wide band signals using uniform linear arrays

971

Hardware implementation of digital watermarking system for real time captured image transmitting

972

Hardware implementation of digitaly controlled colour temperature tuneable white light

973

Hardware implementation of discrete wavelet packet transform for harmonics estimation

974

Hardware implementation of Discrete Wavelet Transform and Inverse Discrete Wavelet Transform on FPGA

975

Hardware implementation of discrete-time neural circuit of largest/smallest signal identification

976

Hardware implementation of Distributed Learning Algorithm for mapping selection for Wireless Physical Layer Network Coding

977

Hardware implementation of distributed speech recognition system front end

978

Hardware implementation of distributed speech recognition system front end

979

Hardware implementation of DNA based cryptography

980

Hardware implementation of droop control for isolated AC microgrids

981

Hardware Implementation of Dynamic Synapse Neural Networks for Acoustic Sound Recognition

982

Hardware implementation of elliptic curve digital signature algorithm (ECDSA) on Koblitz curves

983

Hardware Implementation of EMD Using DSP and FPGA for Online Signal Processing

984

Hardware implementation of encoder for LDPC in CMMB

985

Hardware implementation of enhancement of retinal fundus image using Simulink

986

Hardware implementation of Ethernet based DNP3 data link

987

Hardware implementation of evolutionary digital filters

988

Hardware implementation of fair queuing algorithms for asynchronous transfer mode networks

989

Hardware Implementation of Fast and Robust Star Centroid Extraction With Low Resource Cost

990

Hardware implementation of fast block matching algorithm in FPGA for H.264/AVC

991

Hardware Implementation of Fast Division Algorithm for GF(2^m)

992

Hardware implementation of fast forwarding engine using standard memory and dedicated circuit

993

Hardware implementation of fast neural networks using CPLD

994

Hardware implementation of fast quantum searching algorithms and its application in quantum soft computing and intelligent control

995

Hardware implementation of FAST-based reinforcement learning algorithm

996

Hardware implementation of fast-sequency ordered complex hadamard transform

997

Hardware implementation of feature density distribution algorithm for autonomous robot

998

Hardware implementation of feature extraction from ship´s underwater acoustic signals using LOFAR analysis

999

Hardware implementation of FFT-8086 based system

1000

Hardware implementation of fingerprint image thinning algorithm in FPGA device

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