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1
Memory Efficient Block-Serial Architecture for Programmable, Multi-Rate Multi-Length LDPC Decoder
2
Memory Efficient Calculation of Path Probabilities in Large Structured Markov Chains
3
Memory efficient column-layered decoder design for non-binary LDPC codes
4
Memory efficient data structure for graph representation of DSPF netlist
5
Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes
6
Memory efficient decoder design of nonbinary LDPC codes
7
Memory efficient design of an MPEG-4 video encoder for FPGAs
8
Memory efficient EMS decoding for non-binary LDPC codes
9
Memory efficient error diffusion
10
Memory efficient face recognition using Compressed Phase Component
11
Memory efficient factored abstraction for reinforcement learning
12
Memory efficient fingerprint verification
13
Memory efficient FPGA implementation for flooded LDPC decoder
14
Memory efficient FPGA implementation of hough transform for line and circle detection
15
Memory efficient FPGA implementation of motion and disparity estimation for the multiview video coding
16
Memory efficient global scheduling of real-time tasks
17
Memory efficient hardware design for a 3-spatial layer SVC encoder
18
Memory Efficient Hierarchical Lookup Tables for Mass Arbitrary-Side Growing Huffman Trees Decoding
19
Memory efficient image coding with embedded zero block-tree coder
20
Memory efficient image compressing using lifting scheme
21
Memory efficient implementation of self-corrected min-sum LDPC decoder
22
Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy
23
Memory efficient IP lookup in 100 GBPS networks
24
Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling
25
Memory efficient JPEG2000 architecture with stripe pipeline scheme
26
Memory efficient Laguerre-FDTD scheme for dispersive media
27
Memory efficient layered decoder design with early termination for LDPC codes
28
Memory Efficient LDPC Code Design for High Throughput Software Defined Radio (SDR) systems
29
Memory efficient LDPC decoder design
30
Memory efficient list based Hough transform for programmable digital signal processors with on-chip caches
31
Memory efficient lossless compression of image sequences with JPEG-LS and temporal prediction
32
Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT
33
Memory Efficient Multilevel Discrete Wavelet Transform Schemes for JPEG2000
34
Memory efficient multi-rate regular LDPC decoder for CMMB
35
Memory efficient on-line streaming for multichannel spike train analysis
36
Memory Efficient Parallel Bloom Filters for String Matching
37
Memory Efficient Parallelization for Aho-Corasick Algorithm on a GPU
38
Memory efficient pass-parallel architecture for JPEG2000 encoding
39
Memory efficient pipelined Viterbi decoder with look-ahead trace back
40
Memory efficient programmable processor chip for inverse Haar transform
41
Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams
42
Memory efficient progressive rate-distortion algorithm for JPEG 2000
43
Memory efficient propagation-based watershed and influence zone algorithms for large images
44
Memory Efficient Protocols for Detecting Node replication attacks in wireless sensor networks
45
Memory efficient quadtree wavelet coding for compound images
46
Memory efficient recognition of specific objects with local features
47
Memory Efficient Scattering Matrix Device Simulation By Decomposing The Effect Of Carrier Scattering And Field Acceleration
48
Memory efficient set partitioning in hierarchical tree for color image coding
49
Memory Efficient Set Partitionning in Hierarchical Tree (MESH) for Wavelet Image Compression
50
Memory efficient skeletonization of utility maps
51
Memory efficient software synthesis from dataflow graph
52
Memory efficient software synthesis with mixed coding style from dataflow graphs
53
Memory efficient spectral estimation on parallel computing architectures
54
Memory Efficient Stereoscopy from Light Fields
55
Memory efficient subsequence DTW for Query-by-Example Spoken Term Detection
56
Memory efficient VLSI architecture for lifting-based DWT
57
Memory Efficient, High Speed Implementation of MAX LOG MAP Decoder for CCSDS Turbo codes
58
Memory element based on a layered galvanomagnetic structure
59
Memory element based on the layered galvanomagnetic structure
60
Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS
61
Memory elements utilizing stripe-induced locked hysteresis
62
Memory encoding of object relocation in a hierarchical associative network with theta phase coding
63
Memory energy characterization and optimization for the SPEC2000 benchmarks
64
Memory energy consumption reduction in video coding systems
65
Memory energy management for an enterprise decision support system
66
Memory energy minimization by data compression: algorithms, architectures and implementation
67
Memory enhanced evolutionary algorithms for changing optimization problems
68
Memory Enhanced PSO-Based Optimization Approach for Smart Antennas Control in Complex Interference Scenarios
69
Memory Equilibria in Two-Person Dynamic Games
70
Memory Erasure and Write Field Requirements in HAMR Using L
-FePt Nanoparticles
71
Memory error compensation techniques for JPEG2000
72
Memory error control: beyond parity
73
Memory errors prevention technology for C/C++ program based on probability
74
Memory errors: roll the dice!
75
Memory estimation and allocation algorithms for MDVM system
76
Memory Estimation for High Level Synthesis
77
Memory evolution: Multi-functioning Unified-Random Access Memory (URAM)
78
Memory Expansion Hardware for PDP11 Computers
79
Memory exploration for low power embedded systems
80
Memory exploration for low power, embedded systems
81
Memory exploration utilizing scheduling effects in high-level synthesis
82
Memory Extraction From Dynamic Scattering Junctions in Wave Digital Structures
83
Memory fading Volterra series model for high power infrastructure amplifiers
84
Memory fast-forward: A low cost special function unit to enhance energy efficiency in GPU for big data processing
85
Memory fault diagnosis by syndrome compression
86
Memory Fault Simulator for Static-Linked Faults
87
Memory fault tolerance software mechanisms: design and configuration support through SWN models
88
Memory faults in asynchronous microprocessors
89
Memory foams for robot grippers
90
Memory Footprint Reduction for FPGA Routing Algorithms
91
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters
92
Memory Footprint Reduction with Quasi-Static Shared Libraries in MMU-less Embedded Systems
93
Memory for 40-Mc deltic correlator
94
Memory for Faces in Infants: A Comparison to the Memory for Objects
95
Memory Forensics for Key Evidence Investigations in Case Illustrations
96
Memory forwarding: enabling aggressive layout optimizations by guaranteeing the safety of data relocation
97
Memory function in patients with Parkinson´s disease or subcortical lacunar infarcts evaluated by visual event-related potentials
98
Memory functions for comparative nonlinear dynamics: A new class of dynamic systems unifying chaotic Optofluidics and Electronics
99
Memory functions of neuronal motifs
100
Memory Garbage Collection for an Object-Oriented Processor
101
Memory Generation and Power Distribution In SOC
102
Memory generator method for sizing transistors in RAM/ROM blocks
103
Memory Hardware for High Speed Job Selection
104
Memory hardware support for sparse computations
105
Memory Heat Map: Anomaly detection in real-time embedded systems using memory behavior
106
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
107
Memory Hierarchy Aware Parallel Priority Based Data Structures
108
Memory Hierarchy Configuration Analysis
109
Memory hierarchy considerations for cost-effective cluster computing
110
Memory hierarchy considerations for fast transpose and bit-reversals
111
Memory hierarchy design for a multiprocessor look-up engine
112
Memory hierarchy design for Jetpipeline: to execute scalar and vector instructions in parallel
113
Memory hierarchy exploration for low power architectures in embedded multimedia applications
114
Memory hierarchy for high-performance and energyaware reconfigurable systems
115
Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures
116
Memory hierarchy limitations in multiple-instruction-issue processor design
117
Memory hierarchy management for iterative graph structures
118
Memory Hierarchy Optimization for Large Tridiagonal System Solvers on GPU
119
Memory hierarchy optimization of multimedia applications on programmable embedded cores
120
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
121
Memory hierarchy synthesis of a multimedia embedded processor
122
Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder
123
Memory hierarchy usage estimation for global loop transformations
124
Memory identification of fractional order systems: Background and theory
125
Memory impact on the lifetime of a Wireless Sensor Node using a Semi-Markov model
126
Memory improved proportionate
M
-estimate affine projection algorithm
127
Memory improved proportionate affine projection sign algorithm
128
Memory in nonlinear ionization of transparent dielectrics
129
Memory in Plants Under Low-Intensity Microwave Radiation
130
Memory in processor-supercomputer on a chip: processor design and execution semantics for massive single-chip performance
131
Memory in reservoirs for high dimensional input
132
Memory in Silico: Building a Neuromimetic Episodic Cognitive Model
133
Memory in the fast lane
134
Memory in the small: an application to provide task-based organizational memory for a scientific community
135
Memory in the third dimension
136
Memory integrated noise reduction IC for television
137
Memory Integrity Protection Method Based on Asymmetric Hash Tree
138
Memory intensive multipliers for signal processing
139
Memory interconnection test at board level
140
Memory interference in multimicroprocessor systems with a time-shared bus
141
Memory Interference in Synchronous Multiprocessor Systems
142
Memory Interference Models with Variable Connection Time
143
Memory irradiation measurements for the European SMART-1 spacecraft
144
Memory latency and thread migration challenges for distributed shared memory systems
145
Memory latency effects in decoupled architectures
146
Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module
147
Memory latency in distributed shared-memory multiprocessors
148
Memory latency reduction using an address prediction buffer
149
Memory latency reduction using an address prediction buffer
150
Memory Latency Reduction via Thread Throttling
151
Memory latency-tolerance approaches for Itanium processors: out-of-order execution vs. speculative precomputation
152
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design
153
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design
154
Memory Leak Detection Based on Memory State Transition Graph
155
Memory Leak Detection in FORTRAN Applications Using TAU
156
Memory Leak Detection in Sun Solaris OS
157
Memory leak detection runtime-service for embedded Linux devices
158
Memory Leak Dynamic Monitor Based On HOOK Technique
159
Memory leakage testing using aspects
160
Memory Length in Hyper-heuristics: An Empirical Study
161
Memory Limitation and Multistage Decision Processes
162
Memory loop with Gunn-effect pulse diodes
163
Memory LSI reliability
164
Memory Management Circuit for The Next Generation Optical Drives
165
Memory management for billions of small objects in a distributed in-memory storage
166
Memory Management for Data Localization on OSCAR Chip Multiprocessor
167
Memory management for dataflow programming of multirate signal processing algorithms
168
Memory management for embedded network applications
169
Memory management for high level synthesis applications
170
Memory management for multimedia Quality of Service in resource constrained embedded systems
171
Memory management for real-time appearance-based loop closure detection
172
Memory Management for Real-Time Java: State of the Art
173
Memory management for receive-side enhancement of continuous media QoS
174
Memory management for scalable Web data servers
175
Memory management for user-level network interfaces
176
Memory Management in a Viterbi Decoder
177
Memory management in high-speed communication subsystems
178
Memory management in high-speed Viterbi decoders
179
Memory Management in Java Processor Optimized for RTSJ
180
Memory management in output-buffering packet-switch design
181
Memory management in real-time multiprocessors
182
Memory management of density-based spam detector
183
Memory Management Optimization for Content Routers in DONA
184
Memory management research based on real-time database
185
Memory management scheme for cost-effective disk-on-modules in consumer electronics devices
186
Memory management schemes for radiosity computation in complex environments
187
Memory Management Strategies for Data Serving with RDMA
188
Memory Management Strategies on TCP/IP Performance for Embedded Application
189
Memory Management Support for Multi-Programmed Remote Direct Memory Access (RDMA) Systems
190
Memory Management Support for Tiled Array Organization
191
Memory management techniques for time warp on a distributed memory machine
192
Memory management unit-a new principle for LRU implementation
193
Memory Map of a Knowledge Representation model used for intelligent personalization of learning activities sequences
194
Memory mapped networks: a new deal for distributed shared memories ? the SciFS experience
195
Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors
196
Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms
197
Memory mechanism research for the brain
198
Memory minimisation in control with stochastic automata
199
Memory minimization for tensor contractions using integer linear programming
200
Memory MISER: Improving Main Memory Energy Efficiency in Servers
201
Memory Model = Instruction Reordering + Store Atomicity
202
Memory model effects on application performance for a lightweight multithreaded architecture
203
Memory Model-Aware Testing - A Unified Complexity Analysis
204
Memory modeling for system synthesis
205
Memory modeling for system synthesis
206
Memory Modeling in ESL-RTL Equivalence Checking
207
Memory Modeling-Based Automatic Test Data Generation for String-Manipulating Programs
208
Memory Models for an Application-Specific Instruction-set Processor Design Flow
209
Memory Models for Improving Tabu Search with Real Continuous Variables
210
Memory models for the formal verification of assembler code using bounded model checking
211
Memory Models of Adaptive Behavior
212
Memory module selection for high level synthesis
213
Memory module-level testing and error behaviors for phase change memory
214
Memory motors
215
Memory motors-a new class of controllable flux PM machines for a true wide speed operation
216
Memory neural network algorithm for missile control
217
Memory neuron networks for identification and control of dynamical systems
218
Memory of Janusz Groszkowski (1898 - 1984) - pioneer of radio engineering, world-fame scientist and noble-minded man
219
Memory of neuronal networks: the white noise approach
220
Memory of texture during HDDR processing of NdFeB
221
Memory of texture during HDDR Processing of NdFeB
222
Memory on a chip
223
Memory on the move
224
Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation
225
Memory operation of AlGaAs/GaAs heterostructure FETs with InAs quantum dots in an AlGaAs barrier layer
226
Memory operations of 1T2C-type ferroelectric memory cell with excellent data retention characteristics
227
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs
228
Memory optimisation for hardware induction of axis-parallel decision tree
229
Memory optimisations for high-resolution imaging
230
Memory Optimization Algorithm and Analysis Based on Block Architecture
231
Memory Optimization for Embedded Systems Running H.264/AVC Video Encoder
232
Memory optimization in single chip network switch fabrics
233
Memory optimization of bilateral filter and its hardware implementation
234
Memory optimization of HMAC/SHA-2 encryption
235
Memory optimization of MAP turbo decoder algorithms
236
Memory Optimization Strategy of Audio Processing in MPEG-2 Decoding Chip
237
Memory optimization techniques for multithreaded operating system on wireless sensor nodes
238
Memory optimization techniques for UMTS code generation
239
Memory Optimizations For Fast Power-Aware Sparse Computations
240
Memory optimizations for packet classification algorithms in FPGA
241
Memory Optimized Architecture for Efficient Gauss-Jordan Matrix Inversion
242
Memory optimized lifetime vehicle data acquisition framework
243
Memory Optimized Re-gridding for Non-uniform Fast Fourier Transform on FPGAs
244
Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs
245
Memory or Time: Performance Evaluation for Iterative Operation on Hadoop and Spark
246
Memory ordering: a value-based approach
247
Memory ordering: a value-based approach
248
Memory organization and data layout for instruction set extensions with architecturally visible storage
249
Memory organization for improved data cache performance in embedded processors
250
Memory organization for video algorithms on programmable signal processors
251
Memory organization in a real-time database based on red-black tree structure
252
Memory organization of a single-chip video signal processing system with embedded DRAM
253
Memory organization tradeoffs in computer systems design
254
Memory organization using imperfect bubble chips
255
Memory Organization with Multi-Pattern Parallel Accesses
256
Memory output feedback control with constrained feedback gains for linear time delay systems
257
Memory overbooking and dynamic control of Xen virtual machines in consolidated environments
258
Memory overview and RRAM materials development at SEMATECH
259
Memory Package Error Detection and Correction
260
Memory package with LOC structure using new adhesive material
261
Memory Packaging Material and Assembly Trends
262
Memory palaces to improve quality of life in dementia
263
Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures
264
Memory partitioning and scheduling co-optimization in behavioral synthesis
265
Memory partitioning for multidimensional arrays in high-level synthesis
266
Memory partitioning in Memcached: An experimental performance analysis
267
Memory Paths in Sardinia
268
Memory Patterns Analysis for Discrete-Time Neural Networks with Periodic Coefficients and Time-Varying Transmission Delays
269
Memory performance analysis of SPEC2000C for the Intel(R) Itanium
TM
processor
270
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System
271
Memory performance and retention of an all-organic ferroelectric-like memory transistor
272
Memory Performance and Scalability of Intel´s and AMD´s Dual-Core Processors: A Case Study
273
Memory performance evaluation for networking applications
274
Memory performance in chip-on-chip packages: Optimizing memory/ASIC integration
275
Memory performance model for loops and kernels on Power3 processors
276
Memory performance of a thin-film device based on a conjugated copolymer containing fluorene and chelated europium complex
277
Memory performance optimizations for real-time software HDTV decoding
278
Memory performance prediction for high-performance microprocessors at deep submicrometer technologies
279
Memory persistency
280
Memory Persistency: Semantics for Byte-Addressable Nonvolatile Memory Technologies
281
Memory placement in network compression: Line and grid topologies
282
Memory polynomial based adaptive predistortion for Radio over Fiber systems
283
Memory polynomial digital predistortion for power amplifiers
284
Memory polynomial model for digital predistortion of broadband solid-state radar amplifiers
285
Memory polynomial predistorter based on the indirect learning architecture
286
Memory polynomial with shaped memory delay profile and modeling the thermal memory effect
287
Memory Positioning of Real-Time Code for Smaller Worst-Case Execution Times
288
Memory Power Modeling - A Novel Approach
289
Memory power models for multilevel power estimation and optimization
290
Memory power optimization on different memory address mapping schemas
291
Memory power reduction for the highspeed implementation of turbo codes
292
Memory power reduction for the high-speed implementation of turbo codes
293
Memory Prefetcher Design Based on the SESC Simulator
294
Memory Prefetching Using Adaptive Stream Detection
295
Memory Pressure Balancing on Virtualized Servers
296
Memory Pre-synchronization Technology for Application Migration
297
Memory process and test techniques for known good die
298
Memory processes and motor control in extreme environments
299
Memory processing unit in video decoding system
300
Memory processing units
301
Memory profiling for intra-application data-communication quantification: A survey
302
Memory Profiling using Hardware Counters
303
Memory propagation of negative point-to-plane corona under AC voltage
304
Memory Properties of Nickel Silicide Nanocrystal Layer for Possible Application to Nonvolatile Memory Devices
305
Memory properties using nano-scale phase separation of HfO based dielectrics
306
Memory property of APTMS-mediated Au-SiO
2
core-shell nanocrystal memory
307
Memory Proportionate APA with Individual Activation Factors for Acoustic Echo Cancellation
308
Memory proportionate APSA with individual activation factors for highly sparse system identification in impulsive noise environment
309
Memory protection
310
Memory Protection in Multiprocessing Systems
311
Memory Protection through Dynamic Access Control
312
Memory protection: avoiding the cancer of crashed systems
313
Memory read faults: taxonomy and automatic test generation
314
Memory Reclamation and Compression Using Accurate Working Set Size Estimation
315
Memory reduction and image quality enhancement method for classified vector quantization
316
Memory reduction by Haar wavelet transform for MPEG decoder
317
Memory reduction by Haar wavelet transform for MPEG decoder
318
Memory reduction by intermediate result value encoding for content-based classification
319
Memory reduction ICFO estimation architecture for DVB-T
320
Memory reduction in look-up tables for fast symmetric function generators
321
Memory reduction in MLFMA through target rotation [scattering computation]
322
Memory reduction method of luminance compensation algorithm for mobile AMOLED display applications
323
Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry
324
Memory reduction of fire unit for Petri net controlled multiprocessor
325
Memory reduction of I
DDQ
test compaction for internal and external bridging faults
326
Memory reduction of IFFT using CIM(combined integer mapping) for OFDM transmitters
327
Memory reduction of IFFT using separated CIM (combined integer mapping) method
328
Memory reduction of N-LUT method using sub-principle fringe patterns
329
Memory Reduction Techniques for Logarithmic Number System
330
Memory Reference Behavior of Compiler Optimized Programs on High Speed Architectures
331
Memory reference metrics and instruction trace sampling
332
Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation
333
Memory registration caching correctness
334
Memory Reliability Analysis for Multiple Block Effect of Soft Errors
335
Memory reliability improvements based on maximized error-correcting codes
336
Memory reliability model for accumulated and clustered soft errors
337
Memory Reliability Model for Accumulated and Clustered Soft Errors
338
Memory Repair by Die Stacking with through Silicon Vias
339
Memory repair for high defect densities
340
Memory requirement optimization with loop fusion and loop shifting
341
Memory requirements analysis for PRP and HSR hardware implementations on FPGAs
342
Memory requirements and simulation platform for the implementation of the H.264 encoder modules
343
Memory requirements for future Internet routers with essentially-perfect QoS guarantees
344
Memory requirements for the hardware implementation of decimators
345
Memory requirements of first-order digital filters
346
Memory requirements to balance thus asymptotically full-speedup FFT computation on processor arrays
347
Memory resource considerations in the load balancing of software DSM systems
348
Memory Resource Management for Real-Time Systems
349
Memory Retention Life at Various Environmental and Life Tests
350
Memory safety and race freedom in concurrent programming languages with linear capabilities
351
Memory Saving Discrete Fourier Transform on GPUs
352
Memory savings in Viterbi decoders for (n, 1, m) convolutional codes
353
Memory Scalability Evaluation of the Next-Generation Intel Bensley Platform with InfiniBand
354
Memory scaling: A systems architecture perspective
355
Memory search multiuser detector in DS/CDMA systems
356
Memory search using tunnelling effect [associative memory]
357
Memory security in reconfigurable computers: Combining formal verification with monitoring
358
Memory security management for reconfigurable embedded systems
359
Memory Segmentation and Transfer in Mint Operating System
360
Memory Segmentation to Exploit Sleep Mode Operation
361
Memory servers for multicomputers
362
Memory Servers: A Scope of SOA for High-End Computing
363
Memory SEU simulations using 2-D transport calculations
364
Memory sharing management on virtual private server
365
Memory sharing predictor: the key to a speculative coherent DSM
366
Memory sharing techniques for multi-standard high-throughput FEC decoder
367
Memory size computation for multimedia processing applications
368
Memory size estimation for multimedia applications
369
Memory size reduction for LDPC layered decoders
370
Memory space representation for heterogeneous network process migration
371
Memory specification for reconfigurable computing synthesis tools
372
Memory Speed Analysis of an Optical Flip-Flop Employing a SOA-MZI and a Feedback Loop
373
Memory Speed Analysis of Optical RAM and Optical Flip-Flop Circuits Based on Coupled SOA-MZI Gates
374
Memory speed analysis of optical T-Flip-Flop circuits based on an SOA-MZI and a feedback loop
375
Memory Spot: A Labeling Technology
376
Memory state compressors for giga-scale checkpoint/restore
377
Memory state feedback controller design for singular systems with multiple internal constant point delays
378
Memory state feedback stabilization for nonlinear stochastic time-delay systems
379
Memory state feedback stabilization for singular Markovian jump time-delay systems
380
Memory state transfer optimization for pre-copy based live VM migration
381
Memory State Transient Analysis (MSTA): A New Soft Error Rate Measurement Method for CMOS Memory Elements Based on Stochastic Analysis
382
Memory sub-banking scheme for high throughput MAP-based SISO decoders
383
Memory sub-banking scheme for high throughput turbo decoder
384
Memory subsystem architecture design for multimedia applications
385
Memory Sub-System Optimization on a SIMD Video Signal Processor for Multi-Standard CODEC
386
Memory subsystem simulation in software TLM/T models
387
Memory Subsystems in High-End Routers
388
Memory support design for LU decomposition on the starbridge hyper-computer
389
Memory switching effects in a-Si/c-Si heterojunction bipolar structures
390
Memory switching in amorphous silicon-rich silicon carbide
391
Memory switching of RF permeability in Co/sub 90/Fe/sub 10/ thin films
392
Memory synthesis for high speed DSP applications
393
Memory synthesis for low power ASIC design
394
Memory system behavior of Java-based middleware
395
Memory system characterization of big data workloads
396
Memory system characterization of commercial workloads
397
Memory system compression and its benefits
398
Memory system connectivity exploration
399
Memory System Controlled by Mathematical AIM Model for Robot Vision Equipped with Sleep and Wake Functions
400
Memory system design and implementation for a multiprocessor
401
Memory System Design for a Multi-core Processor
402
Memory System Design for Tolerating Single Event Upsets
403
Memory system design space exploration for low-power, real-time speech recognition
404
Memory system energy: Influence of hardware-software optimizations
405
Memory System for a Dynamically Adaptable Pixel Stream Architecture
406
Memory system for a multi-chip digital computer [United States Patent 3,821,715]
407
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders
408
Memory system optimization of embedded software
409
Memory system prefetching for multi-core and Multi-Threading architecture
410
Memory system reliability improvement through associative cache redundancy
411
Memory system reliability improvement through associative cache redundancy
412
Memory system support for image processing
413
Memory systems for highly parallel computers
414
Memory Systems for Image Processing
415
Memory technologies and data recorder design
416
Memory technologies for 50 nm and beyond
417
Memory Technologies for Mobile Era
418
Memory Technologies for Neural Networks
419
Memory Technologies for sub-40nm Node
420
Memory technologies in the nano-era : challenges and opportunities
421
Memory technologies in the nano-era: challenges and opportunities
422
Memory technology applications for airborne flight data recorder systems
423
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications
424
Memory technology for post CMOS era
425
Memory technology trend and future challenges
426
Memory Technology, Design and Testing
427
Memory test and self-test for deep sub-micron technologies
428
Memory test experiment: industrial results and data
429
Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs
430
Memory test time reduction by interconnecting test items
431
Memory test-debugging test vectors without ATE
432
Memory testing by linear checks
433
Memory testing improvements through different stress conditions
434
Memory testing under different stress conditions: an industrial evaluation
435
Memory testing with a RISC microcontroller
436
Memory testing. characterisation timing and patterns
437
Memory Trace Oblivious Program Execution
438
Memory tracking of the health state of smart products in their lifecycle
439
Memory traffic and data cache behavior of an MPEG-2 software decoder
440
Memory trends
441
Memory trends - Session 20
442
Memory Trends in the 70´s
443
Memory tries to adapt to its surroundings
444
Memory truncation and crosstalk cancellation in transmultiplexers
445
Memory truncation receivers for transmultiplexers
446
Memory Ubiquitous: Providing Memories on Anything, Anywhere - A Case Study for Cooking Support
447
Memory unit design for real time DSP applications
448
Memory usage reduction method for FFT implementations on DSP based embedded system
449
Memory ushering in a scalable computing cluster
450
Memory using diode-coupled bipolar transistor cells
451
Memory utilization in cloud computing using transparency
452
Memory vector quantization by power series expansion [in speech coding]
453
Memory Versus Error Characteristics for Inexact Representations of Linear Orders
454
Memory versus error trade-offs in binary-valued retrieval problems
455
Memory versus error tradeoffs in question-answering systems (Ph.D. Thesis abstr.)
456
Memory versus non-linearity in reservoirs
457
Memory Virtualization for Multithreaded Reconfigurable Hardware
458
Memory yield and complexity of built-in self-repair
459
Memory yield and lifetime estimation considering aging errors
460
Memory yield and repair rate improvement scheme using built in self repair techniques
461
Memory yield improvement - SoC design perspective
462
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models
463
Memory zones for online supermarket shopping
464
Memory, CMOS sensor, and power devices [breaker page]
465
Memory, control and communications synthesis for scheduled algorithms
466
Memory, Difference, and Information: Generative Architectures Latent to Material and Perceptual Plasticity
467
Memory/logic interconnect flexibility in FPGAs with large embedded memory arrays
468
Memory/search RCLA-EC: A CLA-EC for moving parabola problem
469
Memory/speed tradeoffs for look-up table decoding of systematic linear block codes
470
Memory/time optimization of 2-D filters
471
MEMORY: A Matrix-Based Efficient Semantic Web Service Discovery System
472
Memory-
Antipodal Processes: Spectral Analysis and Synthesis
473
Memory-a fast path to one memory
474
Memory-a new era of fast dynamic RAMs (for video applications)
475
Memory-a RAM link for high speed
476
Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems
477
Memory-access-aware data structure transformations for embedded software with dynamic data accesses
478
Memory-adaptive parallel sparse Cholesky factorization
479
Memory-assisted universal compression of network flows
480
Memory-Assisted Universal Source Coding
481
Memory-Attenuated Least Square Filtering and Its Application
482
Memory-Aware Algorithms and Scheduling Techniques: From Multicore Processors to Petascale Supercomputers
483
Memory-Aware and Efficient Ray-Casting Algorithm
484
Memory-aware cooperative CPU-GPU DVFS governor for mobile games
485
Memory-Aware Dynamic Voltage and Frequency Prediction for Portable Devices
486
Memory-aware dynamic voltage scaling for multimedia applications
487
Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling
488
Memory-Aware Energy-Optimal Frequency Assignment for Dynamic Supply Voltage Scaling
489
Memory-Aware Feedback Scheduling of Control Tasks
490
Memory-Aware Green Scheduling on Multi-core Processors
491
Memory-aware i-vector extraction by means of sub-space factorization
492
Memory-Aware List Scheduling for Hybrid Platforms
493
Memory-Aware Loop Paralleling for Coarse-Grained Reconfigurable Architectures
494
Memory-aware mapping and scheduling of tasks and communications on many-core SoC
495
Memory-aware multiple reference frame motion estimation for the H.264/AVC standard
496
Memory-aware NoC Exploration and Design
497
Memory-Aware Optimal Scheduling with Communication Overhead Minimization for Streaming Applications on Chip Multiprocessors
498
Memory-aware optimization of FPGA-based space systems
499
Memory-aware power modeling for PAC DSP core
500
Memory-Aware Scheduling of Multicore Task Sets for Real-Time Systems
501
Memory-aware sizing for in-memory databases
502
Memory-aware SLA-based mechanism for shared-mesh WDM networks
503
Memory-aware system scenario approach energy impact
504
Memory-Aware Task Scheduling with Communication Overhead Minimization for Streaming Applications on Bus-Based Multiprocessor System-on-Chips
505
Memory-bandwidth performance of shared multibuffer switch versus sliding-window switch
506
Memory-bandwidth performance of the sliding-window based routers/switches
507
Memory-bank based radix-2
2
fast fourier transform
508
Memory-Based Algorithms for Abrupt Change Detection in Sensor Data Streams
509
Memory-Based Attention Control for Activity Recognition at a Subway Station
510
Memory-based character recognition using a transformation invariant metric
511
Memory-Based Cluster Sampling for Remote Sensing Image Classification
512
Memory-based codebook model for real-time object detection
513
Memory-based communication facilities and asymmetric distributed shared memory
514
Memory-Based Computation of Inner-Product for Digital Signal Processing Applications
515
Memory-Based Concordancer for Mongolian Toponym
516
Memory-based context-sensitive spelling correction at web scale
517
Memory-based control for recognition of motion environment and planning of effective locomotion
518
Memory-based Control of Nonlinear Dynamic Systems Part I - Design and Analysis
519
Memory-based Control of Nonlinear Dynamic Systems Part II- Applications
520
Memory-based crosstalk canceling CODECs for on-chip buses
521
Memory-Based Data Storing Technologies on Hadoop Distribution File System
522
Memory-based data-driven approach for grapheme-to-phoneme conversion in Bengali text-to-speech synthesis system
523
Memory-based embedded digital ATE
524
Memory-based face recognition for visitor identification
525
Memory-based forecasting of complex natural patterns by retrieving similar image sequences
526
Memory-based Gaussian Mixture Modeling for moving object detection in indoor scene with sudden partial changes
527
Memory-based hardware for resource-constraint digital signal processing systems
528
Memory-based hierarchical task and motion planning
529
Memory-Based High-Performance Optimization for High Concurrent Data-Intensive Problems
530
Memory-Based Human Motion Simulation for Computer-Aided Ergonomic Design
531
Memory-based implementation of a Petri net and its application to a programmable controller
532
Memory-based in situ learning for unmanned vehicles
533
Memory-based label propagation algorithm for community detection in social networks
534
Memory-Based Learning Control
535
Memory-based learning for visual odometry
536
Memory-Based Learning in Intelligent Control Systems
537
Memory-Based List Updating for List Sphere Decoders
538
Memory-based low density parity check code decoder architecture using loosely coupled two data-flows
539
Memory-based moving object extraction for video indexing
540
Memory-based multiprocessor translation-lookaside buffers: multiple paging arenas vs. large size TLB
541
Memory-based navigation using data sequence of laser range finder
542
Memory-based on-line tuning of PID controllers for nonlinear systems
543
Memory-based opportunistic multi-user beamforming
544
Memory-based parsing with parallel marker-passing
545
Memory-based Particle Filter for face pose tracking robust under complex dynamics
546
Memory-based particle filter for real-time object tracking
547
Memory-based passivation approach for 6-DOF haptic rendering of high stiffness virtual environment
548
Memory-Based Passivation Approach for Stable Haptic Interaction
549
Memory-based quantum repeaters with NV centers
550
Memory-based reasoning implemented by wafer scale integration
551
Memory-based recognition of human behavior based on sensory data of high dimensionality
552
Memory-based robot learning
553
Memory-based scheduling for a parallel multifrontal solver
554
Memory-based self-localization using omnidirectional images
555
Memory-based sigma-pi-sigma neural network
556
Memory-based social agent´s actions and mental states design model
557
Memory-based state estimation for handling occlusion during object tracking by Particle Filter
558
Memory-Based Techniques for Task-Level Learning in Robots and Smart Machines
559
Memory-based two-dimensional-parallel differential matched filter correlator for global navigation satellite system code acquisition
560
Memory-Based Vector Quantization of LSF Parameters by a Power Series Approximation
561
Memory-Bounded Ant Colony Optimization With Dynamic Programming and A
∗
Local Search for Generator Planning
562
Memory-cell design in Josephson technology
563
Memory-centric accelerator design for Convolutional Neural Networks
564
Memory-centric architectures: why and perhaps what
565
Memory-centric motion estimator
566
Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor
567
Memory-centric system interconnect design with hybrid memory cubes
568
Memory-centric VDF graph transformations for practical FPGA implementation
569
Memory-centric video processing
570
Memory-configuration and memory-bandwidth in the sliding-window (SW) switch architecture
571
Memory-Conscious Reliable Execution on Embedded Chip Multiprocessors
572
Memory-constrained 3D wavelet transform for video coding without boundary effects
573
Memory-constrained aggregate computation over data streams
574
Memory-constrained Block Processing Optimization for Synthesis of DSP Software
575
Memory-constrained high-order entropy coding by Huffman table sharing and memory allocation
576
Memory-constrained ML-optimal tree search detection
577
Memory-constrained static rate-optimal scheduling of synchronous dataflow graphs via retiming
578
Memory-Constrained Tree Search Detection and New Ordering Schemes
579
Memory-controlled frequency divider for fractional-N synthesisers
580
Memory-core characteristics of cobalt substituted lithium ferrite
581
Memory-correlator cells employing acoustically induced charge hologram in piezoelectric semiconductors
582
Memory-CPU Size Optimization For Embedded System Designs
583
Memory-Efficient 5D Packet Classification At 40 Gbps
584
Memory-Efficient Accelerating Schedule for LDPC Decoder
585
Memory-efficient algorithms for spatial network queries
586
Memory-efficient and fast enumeration of global states
587
Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs
588
Memory-efficient and high-speed LDPC encoder
589
Memory-efficient and high-speed split-radix FFT/IFFT processor based on pipelined CORDIC rotations
590
Memory-efficient and high-throughput decoding of quasi-cyclic LDPC codes
591
Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames
592
Memory-Efficient Architecture for Fast Two-Dimensional Discrete Wavelet Transform
593
Memory-Efficient Architecture for Hysteresis Thresholding and Object Feature Extraction
594
Memory-efficient architecture for JPEG 2000 coprocessor with large tile image
595
Memory-efficient architecture including DWT and EC for JPEG2000
596
Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000
597
Memory-efficient background subtraction for battery-operated surveillance system
598
Memory-efficient belief propagation in stereo matching on GPU
599
Memory-efficient buffering method and enhanced reference template for embedded automatic speech recognition system
600
Memory-efficient centroid decomposition for long time series
601
Memory-efficient circle and ellipse detection algorithm in digital images
602
Memory-Efficient Computation of High-Dimensional Integral Images
603
Memory-Efficient Computation of Persistent Homology for 3D Images Using Discrete Morse Theory
604
Memory-efficient decoding of LDPC codes
605
Memory-Efficient Decoding of Variable Length Codes for Monotonic Sources
606
Memory-Efficient Design Strategy for a Parallel Embedded Integral Image Computation Engine
607
Memory-efficient discrete wavelet transform architecture based on wordlength optimization
608
Memory-efficient FFT architecture using R-LFSR based CORDIC common operator
609
Memory-Efficient Fully Coupled Filtering Approach for Observational Model Building
610
Memory-Efficient Fuzzy Fingerprint Vault based on the Geometric Hashing
611
Memory-efficient H.264/AVC CAVLC for fast decoding
612
Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform
613
Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT
614
Memory-Efficient Hypercube Flow Table for Packet Processing on Multi-Cores
615
Memory-Efficient Image Codec Using Line-based Backward Coding of Wavelet Trees
616
Memory-Efficient Image Databases for Mobile Visual Search
617
Memory-efficient implementation of 3-dimensional zerotree video coding
618
Memory-efficient implementation of a graphics processor-based cluster detection algorithm for large spatial databases
619
Memory-Efficient Implementation of a Rigid-Body Molecular Dynamics Simulation
620
Memory-efficient interconnect optimization
621
Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression
622
Memory-efficient kronecker algorithms with applications to the modelling of parallel systems
623
Memory-efficient Krylov subspace techniques for solving large-scale Lyapunov equations
624
Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures
625
Memory-Efficient Method for Wideband Self-Adjoint Sensitivity Analysis
626
Memory-Efficient Modeling of Reverberation Chambers Using Hybrid Recursive Update Discrete Singular Convolution-Method of Moments
627
Memory-efficient motion estimation design for mobile multimedia applications
628
Memory-efficient multilevel physical optics algorithm for fast computation of scattering from three-dimensional complex targets
629
Memory-Efficient On-Chip Network With Adaptive Interfaces
630
Memory-efficient optimization of Gyrokinetic particle-to-grid interpolation for multicore processors
631
Memory-Efficient Order-Independent Transparency with Dynamic Fragment Buffer
632
Memory-efficient parallel computation of tensor and matrix products for big tensor decomposition
633
Memory-Efficient Parallelization of 3D Lattice Boltzmann Flow Solver on a GPU
634
Memory-efficient parallelization of JPEG-LS with relaxed context update
635
Memory-efficient particle annihilation algorithm for Wigner Monte Carlo simulations
636
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units
637
Memory-Efficient Pipelined Architecture for Large-Scale String Matching
638
Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codes
639
Memory-efficient Radix-2 FFT processor using CORDIC algorithm
640
Memory-efficient ray classification for visibility operations
641
Memory-efficient regular expression matching for Chinese network content audit
642
Memory-Efficient Regular Expression Search Using State Merging
643
Memory-efficient scalable line-based image coding
644
Memory-efficient scalable video encoder architecture for multi-source digital home environment
645
Memory-Efficient Segment-Based Packet-Combining Schemes in Face of Deadlines
646
Memory-Efficient Semi-Quasi Renormalization for Arithmetic Coding
647
Memory-efficient semi-quasi-arithmetic coding
648
Memory-efficient signature matching for ClamAV on FPGA
649
Memory-Efficient Single-Pass GPU Rendering of Multifragment Effects
650
Memory-efficient sum-product decoding of LDPC codes
651
Memory-efficient SURF architecture for ASIC implementation
652
Memory-efficient technique for inclusion of carrier degeneracy in Monte Carlo transport simulation
653
Memory-efficient turbo decoder architectures for LDPC codes
654
Memory-efficient volume ray tracing on GPU for radiotherapy
655
Memory-enabled autonomic resilient networking
656
Memory-enhanced Evolutionary Robotics: The Echo State Network Approach
657
Memory-Enhanced Neural Networks and NMF for Robust ASR
658
Memory-enhanced univariate marginal distribution algorithms for dynamic optimization problems
659
Memory-fast computer memories
660
Memory-fast DRAMs for sharper TV
661
Memory-fast interfaces for DRAMs
662
Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations
663
Memoryful Branching-Time Logic
664
Memory-guided exploration in reinforcement learning
665
Memory-Hazard-Aware K-Buffer Algorithm for Order-Independent Transparency Rendering
666
Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding
667
Memory-Hierarchy-Based Power Reduction for H. 264/AVC Video Decoder
668
Memory-I/O tradeoff and VLSI implementation of lapped transforms for image processing
669
Memory-Intensive Applications on a Many-Core Processor
670
Memory-intensive benchmarks: IRAM vs. cache-based machines
671
Memory-intensive recognition for word articulation training
672
Memory-interference model for multiprocessors based on semi-Markov processes
673
MemoryIO: An Extended I/O Technology in Embedded Systems
674
Memoryless ℋ
∞
controller for a class of differential delay systems
675
Memoryless adaptive robust asymptotic state observers for a class of nonlinear time-delay systems
676
Memoryless adaptive robust state feedback controllers of uncertain dynamical systems with time-varying delays
677
Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding
678
Memoryless coding scheme based on boundary function for distributed sensor systems
679
Memoryless controller design on discrete-time Markovian jump systems with parametric uncertainty and unknown delay
680
Memoryless cooperative graph search based on the simulated annealing algorithm
681
Memoryless decentralised static output feedback variable structure control synthesis for time varying delay interconnected systems
682
Memoryless detection of time-varying deterministic signals in dependent non-Gaussian noise (Corresp.)
683
Memoryless discrete-time detection of a constant signal in m-dependent noise
684
Memoryless discrete-time signal detection in long-range dependent noise
685
Memory-less gain quantization in the EVS codec
686
Memoryless H
∞
controllers for state delayed systems
687
Memoryless individual sequences
688
Memoryless Inference Controls for Statistical Databases
689
Memoryless input-output encoding for networked systems with unknown constant time delay
690
Memoryless linear state or state estimation feedback control for uncertain dynamic delay systems
691
Memoryless locally optimum detection of rate lines
692
Memoryless Multiple Access Channel With Asymmetric Noisy State Information at the Encoders
693
Memoryless non-fragile state feedback control of uncertain multiple time-varying delays system with nonlinearity
694
Memoryless nonlinear system identification with unknown model order
695
Memory-Less Pipeline Dynamic Circuit Design Technique
696
Memoryless pipelined trigonometric processor
697
Memoryless polynomial adaptive predistortion [TV transmitters]
698
Memoryless Polynomial LMS Adaptive Filter for Orbit Object Tracking
699
Memoryless Polynomial RLS Adaptive Filter for Trajectory Target Tracking
700
Memoryless predistortion of nonlinear amplifiers based on Fourier series based models
701
Memoryless quantizer- detectors for constant signals in m-dependent noise
702
Memoryless relay strategies for two-way relay channels
703
Memoryless Relay Strategies for Two-Way Relay Channels: Performance Analysis and Optimization
704
Memoryless representation of Markov processes
705
Memoryless RNS-to-binary converters for the {2
n+1
- 1, 2
n
, 2
n
- 1} moduli set
706
Memoryless robust control for uncertain systems with time-varying delays
707
Memoryless robust control of a class of nonlinear uncertain time-delay system in large-domain
708
Memoryless sampling rate distortion
709
Memoryless sliding mode control of uncertain time-delay systems
710
Memoryless stabilization of linear delay-differential systems
711
Memoryless stabilization of uncertain discrete systems with delayed states and controls
712
Memoryless stabilization of uncertain dynamic delay systems: Riccati equation approach
713
Memoryless stabilization of uncertain linear systems including time-varying state delays
714
Memoryless stabilizing controller designing of uncertain time-delayed systems
715
Memoryless State Feedback Controller Design for Networked Control Systems
716
Memoryless State Feedback Controller Design for Time Delay Systems With Matched Uncertain Nonlinearities
717
Memoryless Static Output Feedback Sliding Mode Control for Nonlinear Systems With Delayed Disturbances
718
Memoryless Viterbi decoder
719
Memoryless Wide-Dynamic-Range CMOS Image Sensor Using Nonfully Depleted PPD-Storage Dual Capture
720
Memory-Link Compression Schemes: A Value Locality Perspective
721
Memory-map selection for firm real-time SDRAM controllers
722
Memory-Mapped File Approach for On-Demand Data Co-allocation on Grids
723
Memory-mapped I/O over dual port BRAM on FPGA
724
Memory-memory-memory Clos-network packet switches with in-sequence service
725
Memory-Optimised Parallel Processing of Hi-C Data
726
Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes
727
Memory-reduced MAP decoding for double-binary convolutional Turbo code
728
MemorySanitizer: Fast detector of uninitialized memory use in C++
729
Memory-Scalable GPU Spatial Hierarchy Construction
730
MemorySense: Reconstructing and ranking user memories on mobile devices
731
Memory-span concepts and the synthesis of sequential machines in feedback shift-register form
732
Memory-State Dependence of Random Telegraph Noise of
Stack ReRAM
733
Memory-system Design Considerations For Dynamically-scheduled Processors
734
Memory-Technologies: Pace-Setters for the IC-Industry
735
Memory-universal prediction of stationary random processes
736
MEMOSEN: multi-radio enabled mobile wireless sensor network
737
Mempack: An order of magnitude reduction in the cost, risk, and time for memory compiler certification
738
MEMPHIS 2000 A Modular Experiment Multiparameter Pulse Height Instrumentation System
739
MEMPHIS 2000-a modular experiment multiparameter pulse height instrumentation system
740
Memphis a Modular Experiment Multiparameter Pulse Height Instrumentation System
741
Memphis Center for Biomedical Engineering in pediatrics: graduate biomedical engineering education with a clinical orientation
742
Memphis: a reuse based OO software development environment
743
Memphis: Finding and fixing NUMA-related performance problems on multi-core platforms
744
MEMPHIS-a fully polarimetric experimental radar
745
MemPhone: From personal memory aid to community memory sharing using mobile tagging
746
MemPick: A tool for data structure detection
747
MemPick: High-level data structure detection in C/C++ binaries
748
Memristance and memcapacitance modeling of thin film devices showing memristive behavior
749
Memristance enhancement by external voltage source
750
Memristance View of Piezoelectricity
751
Memristive analog arithmetic within cellular arrays
752
Memristive and Memcapacitive Characteristics of a Au/Ti–
-InP/InGaAs Diode
753
Memristive based device arrays combined with Spike based coding can enable efficient implementations of embedded neuromorphic circuits
754
Memristive based oscillatory associative and dynamic memories
755
Memristive Behavior in Thin Anodic Titania
756
Memristive Behavior Observed in a Defected Single-Walled Carbon Nanotube
757
Memristive behavior of HF-etched sputtered titania thin films
758
Memristive Behavior of ZnO/Au Film Investigated by a TiN CAFM Tip and Its Model Based on the Experiments
759
Memristive Biosensors Under Varying Humidity Conditions
760
Memristive Circuits for LDPC Decoding
761
Memristive circuits simulate memcapacitors and meminductors
762
Memristive circuits with steady-state mixed-mode oscillations
763
Memristive computational architecture of an echo state network for real-time speech-emotion recognition
764
Memristive computing- multiplication and correlation
765
Memristive crossbar design and test in non-adaptive proactive reconfiguring scheme
766
Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation
767
Memristive device with threshold for synaptic application in Neuromorphic hardwares
768
Memristive devices and systems
769
Memristive devices fabricated with silicon nanowire schottky barrier transistors
770
Memristive devices for stochastic computing
771
Memristive diode bridge with LCR filter
772
Memristive Hebbian Plasticity Model: Device Requirements for the Emulation of Hebbian Plasticity Based on Memristive Devices
773
Memristive multistate pipeline register
774
Memristive nano-crossbar arrays enabling novel computing paradigms
775
Memristive Neuro-Fuzzy System
776
Memristive Properties of Transparent
Thin Films Deposited on ITO Glass at Room Temperature
777
Memristive switching in planar devices based on vanadium dioxide thin films using near IR laser pulses
778
Memristive switching phenomena in a single oxide nanowire
779
Memristive synaptic plasticity in Pr
0.7
Ca
0.3
MnO
3
RRAM by bio-mimetic programming
780
Memristive systems analysis of 3-terminal devices
781
Memristive systems for analog signal processing
782
Memristive Threshold Logic Circuit Design of Fast Moving Object Detection
783
Memristive trans-impedance amplifier (mTIA) and its application to DNA sequencing
784
Memristive XOR for resistive multiplier
785
Memristor Applications for Programmable Analog ICs
786
Memristor applied in delay locked loop for high lock speed and wide frequency range
787
Memristor based adders
788
Memristor based carry lookahead adder architectures
789
Memristor based chaotic circuit with uncertain parameters
790
Memristor based computation-in-memory architecture for data-intensive applications
791
Memristor based crossbar memory array sneak path estimation
792
Memristor based delay element using current starved inverter
793
Memristor based digital-to-analog convertor and its programming
794
Memristor based feedback systems
795
Memristor based high linear range differential pair
796
Memristor based memories: Technology, design and test
797
Memristor based neuromorphic circuit for ex-situ training of multi-layer neural network algorithms
798
Memristor based neuromorphic circuit for visual pattern recognition
799
Memristor based programmable threshold logic array
800
Memristor based STDP learning network for position detection
801
Memristor behavioural modeling and simulations using Verilog-AMS
802
Memristor brains
803
Memristor bridge circuit for neural synaptic weighting
804
Memristor Bridge Synapse-Based Neural Network and Its Learning
805
Memristor Bridge Synapses
806
Memristor cellular automata through belief propagation inspired algorithm
807
Memristor circuit for artificial synaptic weighting of pulse inputs
808
Memristor circuit investigation through a new tutorial toolbox
809
Memristor content addressable memory
810
Memristor Crossbar Architecture for Synchronous Neural Networks
811
Memristor crossbar arrays with junction areas towards sub-10 × 10 nm
2
812
Memristor crossbar based hardware realization of BSB recall function
813
Memristor crossbar based low cost classifiers and their applications
814
Memristor crossbar based multicore neuromorphic processors
815
Memristor Crossbar Based Programmable Interconnects
816
Memristor crossbar based unsupervised training
817
Memristor crossbar memory for hybrid ultra low power hearing aid speech processor
818
Memristor crossbar-based hardware implementation of fuzzy membership functions
819
Memristor Crossbar-Based Hardware Implementation of the IDS Method
820
Memristor Crossbar-Based Neuromorphic Computing System: A Case Study
821
Memristor Drift Model based on conservation of mobile vacancies
822
Memristor emulator based on practical current controlled model
823
Memristor emulator based on single CCII
824
Memristor Emulator for Memristor Circuit Applications
825
Memristor emulator with off-the-shelf solid state components for memristor application circuits
826
Memristor for energy efficient wireless sensor node
827
Memristor in digital logic circuit: Fabrication and proof of concept
828
Memristor in neuromorphic computing
829
Memristor load current mirror circuit
830
Memristor Logic Operation Gate With Share Contact RRAM Cell
831
Memristor lookup table (MLUT)-based asynchronous nanowire crossbar architecture
832
Memristor macromodel and its application to neuronal spike generation
833
Memristor measurements and simulations
834
Memristor memory trade-offs and design considerations
835
Memristor model based on fuzzy window function
836
Memristor Model Comparison
837
Memristor model for massively-parallel computations
838
Memristor Modeling -- Static, Statistical, and Stochastic Methodologies
839
Memristor modelling
840
Memristor models and circuits for controlling Process-V
DD
-Temperature variations
841
Memristor models for chaotic neural circuits
842
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
843
Memristor Multiport Readout: A Closed-Form Solution for Sneak Paths
844
Memristor panic — A survey of different device models in crossbar architectures
845
Memristor pattern recogniser: isolated speech word recognition
846
Memristor pinched hysteresis loops: Touching points, Part I
847
Memristor pinched hysteresis loops: Touching points, Part II
848
Memristor plasticity enables emergence of synchronization in neuromorphic networks
849
Memristor PUF—A Security Primitive: Theory and Experiment
850
Memristor PUFs: A new generation of memory-based Physically Unclonable Functions
851
Memristor Resistance Modulation for Analog Applications
852
Memristor SPICE model and crossbar simulation based on devices with nanosecond switching time
853
Memristor Spice model for designing analog circuit
854
Memristor SPICE model with tukey window function for stable analysis
855
Memristor state to logic mapping for optimal noise margin in memristor memories
856
Memristor state-space embedding
857
Memristor structures based on tunnel-thin organic dielectric and porous silicon layers
858
Memristor synaptic dynamics´ influence on synchronous behavior of two Hindmarsh-Rose neurons
859
Memristor system properties and its design applications to circuits such as nonvolatile memristor memories
860
Memristor technology in future electronic system design
861
Memristor to control delay of delay element
862
Memristor: From Basics to Deployment
863
Memristor: Modeling read and write operations
864
Memristor: Part I—The Underlying Physics and Conduction Mechanism
865
Memristor: Part II–DC, Transient, and RF Analysis
866
Memristor: the enabler of computation-in-memory architecture for big-data
867
Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design
868
Memristor-based activation circuit for long-term memories in cognitive architectures
869
Memristor-Based Adaptive Coupling for Consensus and Synchronization
870
Memristor-based approximated computation
871
Memristor-based arithmetic
872
Memristor-based balanced ternary adder
873
Memristor-based cell design and digital logical operations implementation
874
Memristor-based cellular nanoscale networks: Theory, circuits, and applications
875
Memristor-based cellular nonlinear networks with belief propagation inspired algorithm
876
Memristor-Based Cellular Nonlinear/Neural Network: Design, Analysis, and Applications
877
Memristor-based Center-Of-Gravity (COG) defuzzifier circuit
878
Memristor-Based Chaotic Circuit for Text/Image Encryption and Decryption
879
Memristor-based comparator with programmable hysteresis
880
Memristor-based devices for sensing
881
Memristor-based filtering applications
882
Memristor-based fine resolution programmable resistance and its applications
883
Memristor-based IMPLY logic design procedure
884
Memristor-based linear feedback shift register based on material implication logic
885
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies
886
Memristor-based modified recoded-multiplicand systolic serial-parallel multiplier
887
Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training
888
Memristor-based multilevel memory
889
Memristor-Based Multithreading
890
Memristor-based neural circuits
891
Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions
892
Memristor-based neural network PID controller for buck converter
893
Memristor-based neuron circuit and method for applying learning algorithm in SPICE?
894
Memristor-Based Nonvolatile Random Access Memory: Hybrid Architecture for Low Power Compact Memory Design
895
Memristor-based oscillator using Deboo integrator
896
Memristor-based parallel sorting approach using one-dimensional cellular automata
897
Memristor-based pixel for event-detection vision sensor
898
Memristor-based programmable delay element
899
Memristor-based random access memory: The delayed switching effect could revolutionize memory design
900
Memristor-based reactance-less oscillator
901
Memristor-based redundant binary adder
902
Memristor-based relaxation oscillators using digital gates
903
Memristor-based reservoir computing
904
Memristor-based stored-reference receiver - the UWB solution?
905
Memristor-based synapse design and a case study in reconfigurable systems
906
Memristor-based synapse design and training scheme for neuromorphic computing architecture
907
Memristor-based synapses and neurons for neuromorphic computing
908
Memristor-based synaptic networks and logical operations using in-situ computing
909
Memristor-capacitor based startup circuit for voltage reference generators
910
Memristor-CMOS interfacing circuit SPICE model
911
Memristor-CMOS reconfigurable multiplier architecture
912
Memristor-less current- and voltage-controlled meminductor emulators
913
Memristor-MOS hybrid circuit redundant multiplier
914
Memristors and Bernoulli dynamics
915
Memristors and memristive circuits - an overview
916
Memristors as non-linear behavioral models for passive inter-modulation simulation
917
Memristors as non-linear behavioral models for passive inter-modulation simulation
918
Memristors as synapse emulators in the context of event-based computation
919
Memristors based on an organic monolayer of molecules and a thin film of solid electrolytes
920
Memristors Empower Spiking Neurons With Stochasticity
921
Memristors for digital, memory and neuromorphic circuits
922
Memristors for energy-efficient, bioinspired processing
923
Memristors With Flexible Electronic Applications
924
Memristors, memristive devices and systems in nano era
925
Memristors: Devices, Models, and Applications [Scanning the Issue]
926
Memristors: The fourth fundamental circuit element
927
Memristors-based NMOS logic circuits
928
Memristors-based Ternary Content Addressable Memory (mTCAM)
929
Memristor-The missing circuit element
930
MEMS
931
MEMS & MOEMS reliability: wafer-level packaging and low-temperature processing issues
932
MEMS & Sensors
933
MEMS μ-wire magnetic field detection method@CERN
934
MEMS — BiCMOS monolithic integration
935
MEMS 2004 Technical Program Committee
936
MEMS 2005 - Miami - Technical Digest - Cover
937
MEMS 2005 - Miami - Welcome Page
938
MEMS 2005 Miami - Back Cover
939
MEMS 2005 Technical Program Committee
940
MEMS 2008
941
MEMS 2008 Technical Program Committee
942
MEMS 2009
943
MEMS 2009 Program Schedule
944
MEMS 2010
945
MEMS 2011
946
MEMS 2011 author index
947
MEMS 2011 keyword index
948
MEMS 2011 program schedule
949
MEMS 2012 author index
950
MEMS 2012 keyword index
951
MEMS 2012 program schedule
952
MEMS 2012–register now
953
MEMS 2015
954
MEMS 2-bit phase-shifter failure mode and reliability considerations for large X-band arrays
955
MEMS 2D matrix switch
956
MEMS 30µm-thick W-band waveguide switch
957
MEMS 30µm-thick W-band waveguide switch
958
MEMS 3-axis inertial sensor process
959
MEMS 3D optical mirror/scanner
960
MEMS absolute pressure sensor on a flexible substrate
961
MEMS Acceleration Sensor With Large Dynamic Range and High Sensitivity
962
MEMS acceleration switch capable of increasing threshold acceleration
963
MEMS Accelerometer Based Nonspecific-User Hand Gesture Recognition
964
MEMS accelerometer based on Molecular Electronic Transducers using Ionic Liquid
965
MEMS accelerometer based system for motion analysis
966
MEMS Accelerometer Fabricated Using Printed Circuit Processing Techniques
967
MEMS accelerometer with all-optical readout based on twin-defect photonic crystal waveguide
968
MEMS accelerometer with mechanical amplification mechanism for enhanced sensitivity
969
MEMS Accelerometer with Screen Printed Piezoelectric Thick Film
970
MEMS accelerometer with two thin film piezoelectric read-out
971
MEMS accelerometer with two thin film piezoelectric read-out
972
MEMS accelerometers and their bio-applications
973
MEMS accelerometers on polyimides for failure assessment in aerospace systems
974
MEMS acoustic array embedded in an FPGA based data acquisition and signal processing system
975
MEMS acoustic emission sensor with mechanical noise rejection
976
MEMS acoustic sensors for totally implantable hearing aid systems
977
MEMS acoustic sensors for totally implantable hearing systems
978
MEMs activity at Rochester Institute of Technology
979
MEMS Actuated Piezoelectrically with AlN Films
980
MEMS actuated spherical retroreflector for free-space optical communications
981
MEMS actuation for a continuously tunable optical buffer
982
MEMS actuator array as a neuro-physiological testing tool
983
MEMS Actuators for Aligning and Tuning Optical Microcavities on Atom Chips
984
MEMS AD/DA Converters
985
MEMS an alternative paradigm for ATE RF designers
986
MEMS and combined MEMS/LC technology for mm-wave electronic scanning
987
MEMS and energy theory of stochastic signals: Signal rhythmic and time measurement problem
988
MEMS and fiber optics sensor-based wearable interface for medical applications
989
MEMS and fiber optics sensor-based wearable interface for medical applications
990
MEMS and J2ME based acceleration real-time measurement and monitoring system for fuel cell city bus
991
MEMS and lab on chip: Interfacing macro to nano world
992
MEMS and MEMS based strain gauge load cells — A review
993
MEMS and microsystems for navigation, sensing, and spectral processing
994
MEMS and Nano Technology for the Handheld, Portable Electronic and the Automotive Markets
995
MEMS and nano/bio technologies
996
MEMS and NEMS - systems, devices, and structures
997
MEMS and NEMS technologies for wireless communications
998
MEMS and NEMS with integrated cavity optomechanical readout
999
MEMS and NEMS: Systems, devices, and structures [Book Review]
1000
MEMS- and probe-based mass data storage in conventional CMOS
