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1
Test of the ITER TF insert and Central Solenoid Model Coil
2
Test of the lightning indirect effects on an aircraft
3
Test of the MECS IHT system with bovine tongues
4
Test of the Model for the Generation of Attenuation Time Series based on ITALSAT Measurements
5
Test of the NbAl insert and ITER central solenoid model coil
6
Test of the probability formulation of the Synthetic Storm Technique against reliable measurements of rain rate and rain attenuation
7
Test of the reachability of a robot to an object
8
Test of the REX-RFQ and status of the front part of the REX-ISOLDE linac
9
Test of the thermal-noise hypothesis in m.o.s.f.e.t.s
10
Test of the transport properties of a helical electrostatic quadrupole and quasi-octupole
11
Test of the VCSEL driver based on Verilog-A VCSEL model
12
Test of thermal stability of magnet wire enamel
13
Test of Tracing Performance with an Active Handheld Micromanipulator
14
Test of two 1.8 m SSC model magnets with iterated design
15
Test of two prototype high-temperature superconducting transmission cables
16
Test of Urban Road Traffic Facilities on the Driving Safety
17
Test of very fast kicker for TESLA damping ring
18
Test of wettability of lead-free solders
19
Test of YBCO thin films based fault current limiters with a newly designed meander
20
Test on acoustic resonance characteristic of PTFE micro/nano-aperture membrane for nanobiomedical application
21
Test on antennas in a Reverberating Chamber and comparison with anechoic chamber
22
Test on automobile engine noise production source and impact based on sound intensity method
23
Test on electromagnetic transient in an operating UHVDC converter station
24
Test on EM Bacteria Applied in Treating Landscape Water
25
Test on Evaluation Index of Deformation Performance for Polyester Fiber Reinforced Asphalt Concrete
26
Test on Lightning Characteristics of Electronic Equipment´s Power Supply
27
Test on Mechanical Properties of Cemented Soils Using Secondary Development Data Acquisition Test System
28
Test on the Economics Cobweb Model by Using Eviews Programming
29
Test on the Validity of Futures Market´s High Frequency Volume and Price on Forecast
30
Test operation of ball-screw-type tuner for low-los high-gradient superconducting cavity at 77 K
31
Test operation of phosphoric acid fuel cell plant
32
Test operation-driven approach on building regression testing environment
33
Test operations of stand alone Photovoltaic Power Generation Systems and calculation of their scale merit
34
Test optimization of bus-structured SoCs using embedded processor
35
Test Optimization Using Software Virtualization
36
Test oracles based on artificial neural networks and info fuzzy networks: A comparative study
37
Test oracles based on metamorphic relations for image processing applications
38
Test orchestration a framework for Continuous Integration and Continuous deployment
39
Test order for class-based integration testing of Java applications
40
Test order for inter-class integration testing of object-oriented software
41
Test oriented formal model of SDN applications
42
Test oscillator for study of drive level dependence of quartz crystals
43
Test outsourcing - a subcontract manufacturer´s perspective
44
Test Paper Problem Solved by Binary Ant Colony Algorithm
45
Test Parameters Optimization Based on Newton-Gaussian Method in Analog Signature Analysis
46
Test particle interaction of a sheet electron beam with a Gaussian propagating radiation beam from a gyrotron
47
Test particle simulation of relativistic electrons interacting with EMIC triggered emissions in the radiation belts
48
Test path generation and test scheduling for self-testable designs
49
Test path selection based on effective domains
50
Test Path Selection for Capturing Delay Failures Under Statistical Timing Model
51
Test path simulation and characterisation
52
Test pattern and test configuration generation methodology for the logic of RAM-based FPGA
53
Test pattern based evaluation of ringing and blur in JPEG and JPEG2000 compressed images
54
Test Pattern Compression Based on Pattern Overlapping
55
Test pattern compression based on pattern overlapping and broadcasting
56
Test pattern compression using prelude vectors in fan-out scan chain with feedback architecture
57
Test pattern decompression in parallel scan chain architecture
58
Test pattern decompression using a scan chain
59
Test Pattern Dependent FPGA Based System Architecture for JTAG Tests
60
Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIM
61
Test pattern embedding in sequential circuits through cellular automata
62
Test pattern for microwave dielectric properties of SrBi
2
Ta
2
O
9
63
Test pattern for supply current test of open defects by applying time-variable electric field
64
Test pattern generation and clock disabling for simultaneous test time and power reduction
65
Test pattern generation and clock disabling for test time and power reduction
66
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults
67
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
68
Test pattern generation and signature analysis for burst errors
69
Test Pattern Generation Based On Arithmetic Operations
70
Test Pattern Generation for API Faults in RAM
71
Test pattern generation for API faults in RAM
72
Test pattern generation for benchmark circuits using LFSR
73
Test pattern generation for circuits with asynchronous signals based on scan
74
Test pattern generation for circuits with tri-state modules by
Z
-algorithm
75
Test pattern generation for column compression multiplier
76
Test pattern generation for combinatorial multi-valued networks based on generalized D-algorithm
77
Test pattern generation for current testable faults in static CMOS circuits
78
Test pattern generation for droop faults
79
Test pattern generation for I
DDQ
: increasing test quality
80
Test pattern generation for logic crosstalk faults in VLSI circuits
81
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays
82
Test pattern generation for multiple output digital circuits using cubical calculus and Boolean differences
83
Test pattern generation for multiple stuck-at faults
84
Test pattern generation for path delay faults in synchronous sequential circuits using multiple fast clocks and multiple observation times
85
Test pattern generation for power supply droop faults
86
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
87
Test pattern generation for sequential circuits on a network of workstations
88
Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation
89
Test pattern generation for signal integrity faults on long interconnects
90
Test pattern generation for static burn-in based on equivalent fault model
91
Test Pattern Generation for Stuck-Open Faults Using Stuck-At Test Sets in CMOS Combinational Circuits
92
Test pattern generation for the combinational representation of asynchronous circuits
93
Test pattern generation for timing-induced functional errors in hardware-software systems
94
Test pattern generation for width compression in BIST
95
Test pattern generation for worst-case crosstalk faults in DSM chips using Genetic Algorithm
96
Test pattern generation in presence of unknown values based on restricted symbolic logic
97
Test Pattern Generation of Relaxed
-Detect Test Sets
98
Test pattern generation system for delay faults using a high speed simulation processor ´SP´
99
Test pattern generation using Boolean satisfiability
100
Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST
101
Test pattern generation with restrictors
102
Test pattern generator and logic simulator based on object oriented PSPICE net list
103
Test Pattern Generator for Delay Faults
104
Test pattern generator for hybrid testing of combinational circuits
105
Test pattern generator modification method for BIST
106
Test pattern generators for distributed and embedded built-in self-test at register transfer level
107
Test pattern length required to reach the desired fault coverage
108
Test pattern optimization using proper in mixed-mode technique
109
Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment
110
Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption
111
Test Pattern Selection for Defect-Aware Test
112
Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks
113
Test pattern selection to optimize delay test quality with a limited size of test set
114
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
115
Test patterns for EPROMs
116
Test patterns for ICs that are both secure and have very high coverage
117
Test Patterns for Verilog Design Error Localization
118
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
119
Test phantoms for color flow imaging systems [biomedical ultrasonics]
120
Test pin count reduction for NoC-based Test delivery in multicore SOCs
121
Test plan automation for power transformer protective relay commissioning
122
Test Plan for Experiments to Provide Preliminary End-to-End Communication System Performance of an A
123
Test plan generation and concurrent scheduling of tests in the presence of conflicts
124
Test planning — A comparison between the decision tree and the Belief Network approach
125
Test planning and design space exploration in a core-based environment
126
Test planning and test access mechanism design for stacked chips using ILP
127
Test planning and test resource optimization for droplet-based microfluidic systems
128
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
129
Test planning for mixed-signal SOCs with wrapped analog cores
130
Test planning for modular testing of hierarchical SOCs
131
Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs
132
Test plant as the first step towards commercialization of SMES for utilities
133
Test platform for fault tolerant systems design properties verification
134
Test platform for hybrid electric power systems: Development of a HIL test platform
135
Test platform for hybrid electric power systems: Use for design project for students
136
Test Platform for Millimeter-wave Amplifier Linearity Characterization
137
Test platform for synchrophasor based wide-area monitoring and control applications
138
Test platform of auto wheel speed sensor based on labVIEW
139
Test platform of smart grids with renewable energy systems and plug-in hybrid electric vehicles
140
Test platform to pitch angle using hardware in loop
141
Test point insertion based on path tracing
142
Test point insertion for an area efficient BIST
143
Test point insertion for compact test sets
144
Test point insertion that facilitates ATPG in reducing test time and data volume
145
Test point insertion using functional flip-flops to drive control points
146
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops
147
Test point insertion: scan paths through combinational logic
148
Test point optimization for model-based fault diagnosis expert system
149
Test point optimization for model-based fault diagnosis of satellite aviation system
150
Test point optimization of control moment gyro (CMG) based on multi-signal flow model and improved genetic algorithm
151
Test point optimization process for a real-time vibration monitoring system on a differential axle fixed rig
152
Test Point Placement to Simplify Fault Detection
153
Test point selection based on functional simulation and FMMEA for an electronic system on PHM
154
Test point selection for analog fault diagnosis of unpowered circuit boards
155
Test point selection methods for the self-testing based analogue fault diagnosis system
156
Test point selection of analog circuits based on fuzzy theory and ant colony algorithm
157
Test point selection strategy under unreliable test based on heuristic particle swarm optimization algorithm
158
Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods
159
Test Point Specific k Estimation for kNN Classifier
160
Test points selection process and diagnosability analysis of analog integrated circuits
161
Test Policy: Gaining Control on IT Quality and Processes
162
Test port cable instability and VNA measurement errors
163
Test power aware STUMP BIST
164
Test Power IR Drop Closure Flow for NetComposer-I Platform Design
165
Test power minimization of VLSI circuits: A survey
166
Test power optimization techniques for CMOS circuits
167
Test Power Reduction by Blocking Scan Cell Outputs
168
Test power reduction in compression-based reconfigurable scan architectures
169
Test power reduction through minimization of scan chain transitions
170
Test power reduction via deterministic alignment of stimulus and response bits
171
Test power reduction with multiple capture orders
172
Test power reductions through computationally efficient, decoupled scan chain modifications
173
Test power: a big issue in large SOC designs
174
Test preparation and fault analysis using a bottom-up methodology
175
Test preparation for high coverage of physical defects in CMOS digital ICs
176
Test preparation methodology for high coverage of physical defects in CMOS digital ICs
177
Test prioritization using system models
178
Test problems and representations for graph evolution
179
Test problems for validation of space charge codes
180
Test procedure and acceptance criteria for PD commissioning testing of transmission class cables
181
Test procedure and specifications for component susceptibility to electrostatic discharges
182
Test procedure and test circuit considerations for on load tap changer dynamic resistance measurement
183
Test procedure development for automotive conducted susceptibility and conducted emissions
184
Test Procedure for Detectors with Resistance Coupled Output
185
Test procedure for very high speed spindle motors
186
Test Procedure Language Development
187
Test procedure of indoor lighting LED luminaires based on step-stress accelerated degradation test
188
Test Procedure Optimization for Layered Protocol Implementations
189
Test procedures and lifetime data analysis for electro-thermal endurance characterisation of EPR-insulated cables
190
Test procedures and performance assessment of mobile fading channel simulators
191
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
192
Test procedures for conducted transient immunity testing for low frequency energy meters
193
Test procedures for predicting surface voltages on inhabited garments
194
Test procedures for protection devices
195
Test procedures for proton-induced single event latchup in space environments
196
Test Procedures for Proton-Induced Single Event Latchup in Space Environments
197
Test procedures for the evaluation of defect tolerance of electrically-stressed polymers
198
Test Process Improvement with Documentation Driven Integration Testing
199
Test process optimization: closing the gap in the defect spectrum
200
Test processor ASIC design
201
Test processor chip design with complete simulation result including reseeding technique
202
Test profile design for avionics Full-Duplex Switched Ethernet
203
Test profiling for usage models by deriving metrics from component-dependency-models
204
Test program and ATE station dependencies: Have we learned anything from the past, or are we doomed to repeat it?
205
Test program development in VLSI testing
206
Test program development using multiple test strategies
207
Test program for Honeywell/DND helicopter integrated navigation system (HINS)
208
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices
209
Test Program Generation for Functional Verification of PowePC Processors in IBM
210
Test program generation for mixed-signal integrated circuits based on automata network
211
Test program of copper and aluminum electrical connectors under ageing conditions common to renewable energy systems
212
Test program of multi-junction GaAs/Ge solar array coupons with combined space environmental exposures
213
Test program offload using CRATE
214
Test program set (TPS) migration
215
Test program set data collection and data mining
216
Test program set rehosting
217
Test program set software development using the rational Booch method
218
Test program set/document management system
219
Test program sets and vertical testability
220
Test program sets on the flightline - a case study verifying jammers
221
Test program sets-a new approach
222
Test program structure and development on the Common Test Station
223
Test program synthesis for path delay faults in microprocessor cores
224
Test program to determine the mechanical properties of the NCSX modular coils
225
Test program transportability using a common ATE framework
226
Test programming environment in a modular, open architecture test system
227
Test programming in an ABBET signal-oriented environment
228
Test Propagation Through Modules and Circuits
229
Test Purpose Generation for Timed Protocol Testing
230
Test purpose-based test generation for web applications
231
Test purposes: adapting the notion of specification to testing
232
Test Q&A: Behind closed doors with test experts
233
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
234
Test quality and fault risk in digital filter datapath BIST
235
Test quality and yield analysis using the DEFAM defect to fault mapper
236
Test Quality Feedback Improving Effectivity and Efficiency of Unit Testing
237
Test quality for high level structural test
238
Test quality improvement by physical testability enhancement
239
Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case study
240
Test Quality Measurement Using TBPP-R
241
Test quality of asynchronous circuits: a defect-oriented evaluation
242
Test quality: required stuck-at fault coverage with the use of I
DDQ
testing
243
Test Question Classification and Duplicate Checking Based on Course Knowledge Point
244
Test radar demonstration of the orbitron maser
245
Test Reactive Systems with Buchi Automata: Acceptance Condition Coverage Criteria and Performance Evaluation
246
Test ready core design for a DSP core
247
Test ready core design for TeakLite core
248
Test Reconfiguration for Service Oriented Applications
249
Test Redundancy Measurement Based on Coverage Information: Evaluations and Lessons Learned
250
Test register insertion with minimum hardware cost
251
Test reliability and software maintenance
252
Test Report on a Fully Supercharged Generator [includes discussion]
253
Test Reports of the DAQ System with the Tracking Detector Prototype for MECO Experiment
254
Test requirement analysis for low cost hierarchical test path construction
255
Test Requirements and Performance Evaluation for Both Resistive and Inductive Superconducting Fault Current Limiters for 22.9 kV Electric Distribution Network in Korea
256
Test requirements for embedded core-based systems and IEEE P1500
257
Test requirements model (TeRM) overview and status
258
Test requirements: Selecting the optimal AC power source technology for your application: Linear or switch mode technology considerations and trade-offs
259
Test research for effects of the cab suspension system on heavy vehicle ride Comfort
260
Test research in Japan
261
Test research of environment influence to tan δ of capacitive equipment
262
Test research of the influence of the rate of water content on the consolidation and creep of the soft clay
263
Test Research on Burning Characteristics of Flooring Decorative Materials Ignited by Accelerant
264
Test Research on Electrostatic Decay in Fuel Tanks System Filled with Reticulated Polyurethane Foam
265
Test research on horizontal shear wave in grounding flat steel
266
Test Research on Operation Life of Silicone Rubber Composite Insulators
267
Test Research on Optimal Application of BMA Modified Ashphalt
268
Test research on overvoltage withstanding characteristics of control cables
269
Test research on performance of water mist fire-resistant and smoke-abatement
270
Test research on power transformer winding deformation by FRA method
271
Test Research on the Construction of Dynamic Performance Detection Platform for High-Grade Numerical Control Machines
272
Test research on the influence of pile group vertical bearing characteristic due to water scouring
273
Test research on the kinetic characteristic of dust particles under different electric field
274
Test Research on UWB Effects and Mechanism of Radio Fuze
275
Test research on vehicle information wireless communication system
276
Test resource management
277
Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints
278
Test resource partitioning
279
Test resource partitioning and optimization for SOC designs
280
Test resource partitioning and reduced pin-count testing based on test data compression
281
Test resource partitioning based on efficient response compaction for test time and tester channels reduction
282
Test resource partitioning for SOCs
283
Test resource partitioning: a design and test issue
284
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register
285
Test response compaction using arithmetic functions
286
Test response compaction using multiplexed parity trees
287
Test Response Compaction via Output Bit Selection
288
Test response compactor with programmable selector
289
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring
290
Test response compression based on Huffman coding [logic IC testing]
291
Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction
292
Test responses compaction in accumulators with rotate carry adders
293
Test result analysis and diagnostics for finite state machines
294
Test Result of a Full-Size
Conductor Developed for the ITER TF Coils
295
Test result of full size 40 kA NET/ITER conductor in the FENIX test facility
296
Test result of individual ASTROMAG test coils with aluminum stabilized superconductor
297
Test Result of L2 handover scheme for SMART Highway
298
Test result of microgrid management function in KERI pilot plant
299
Test results and analysis of a low cost core GPS receiver for time transfer applications
300
Test results and analysis of current limiting characteristics in conduction cooled Bi2223 fault current limiter
301
Test Results and Analysis of LQS03 Third Long
Quadrupole by LARP
302
Test results and analysis of two European full-size conductor samples for ITER
303
Test results and circuit breaker behavior
304
Test results and commercialization plans for long life Stirling generators
305
Test results and design considerations for a 500 MHz, 500 kWatt vacuum window for CESR-B
306
Test results and initial operating experience for the BPA 500 kV thyristor controlled series capacitor design, operation, and fault test results
307
Test results and initial operating experience for the BPA 500 kV thyristor controlled series capacitor-modulation, SSR and performance monitoring
308
Test Results and Investigation of Tcs Degradation in Japanese ITER CS Conductor Samples
309
Test results and irradiation performances of 3-D circuits developed in the framework of ATLAS hybrid pixel upgrade
310
Test results and operational characteristics of prototype SSCL half cell
311
Test results and perspectives of the cluster test program
312
Test results and potential for upgrade of the 45 T hybrid insert
313
Test results and preliminary conclusions regarding 0.1Hz VLF testing on very long, mixed distribution feeders of 13.8 to 33 kV system voltage
314
Test results and system performance
315
Test Results and Torque Improvement of the 50-kW Switched Reluctance Motor Designed for Hybrid Electric Vehicles
316
Test Results and Validation of the FeedMAP Framework with ADAS Applications
317
Test results dealing with contact resistance in vacuum interrupters
318
Test Results for a 1.5 T MRI System Utilizing a Cryogen-free YBCO Magnet
319
Test Results for a 19 kW, 1497 MHz Klystron for Accelerators
320
Test results for a Bi-2223 HTS racetrack coil generator applications
321
Test results for a heat-treated 4-cell 805-MHz superconducting cavity
322
Test results for a high field (13 T) Nb
3
Sn dipole
323
Test results for a high-voltage multi-junction-cell concentrator array direct-driving an electric thruster
324
Test results for a linear tapered slot antenna with varying slot-line lengths and mounting configurations
325
Test results for a Nb/sub 3/Sn dipole magnet
326
Test results for a subscale (100 kA) SMES splice
327
Test results for an advanced conductor for the Wendelstein 7-X magnet system
328
Test results for an off the shelf GPS/INS during approach and landing testing of the X-40A
329
Test Results for Energy Savings
330
Test results for HD1, a 16 tesla Nb
3
Sn dipole magnet
331
Test results for HF RFID Antenna system tuning in metal environment
332
Test Results for HINS Focusing Solenoids at Fermilab
333
Test results for laboratory scale inductive high-T
c
superconducting fault current limiters
334
Test Results for LHC Insertion Region Dipole Magnets
335
Test results for prototypes of the twin aperture dipoles for the LHC insertion region
336
Test results for the development of a novel region-based DOCSIS compliant cable plant system and protocol to optimally reduce contention mini-slot collisions and to support QoS on DOCSIS 1.1/1.2 networks
337
Test Results for the East Central Solenoid Model Coil
338
Test Results for the Electron Lens Superconducting Magnets at RHIC
339
Test results for the multiple spot beam antenna project “Medusa”
340
Test results for the WAAS Signal Quality Monitor
341
Test results for three prototype models of a linear induction launcher
342
Test results for transient excitation boosting at Grand Coulee
343
Test results for upgraded switching mode power supplies for the multipole elements in the Bates South Hall Ring Project
344
Test results from 1.8-m SSC model dipoles
345
Test results from a 1.3 GHZ, 10 MW, high efficiency multiple beam klystron for XFEL
346
Test results from a 1319-nm laser radar with RF pulse compression
347
Test Results from a 15 Kw Air-Independent Stirling Power Generator
348
Test results from a multi-frequency bathymetric synthetic aperture sonar
349
Test results from a tactical grade IMU using fiber optic gyros and quartz accelerometers
350
Test results from a tower VOR over a forest area
351
Test Results from Coaxial Cavities for Separated-Orbit Cyclotrons
352
Test results from high intensity discharge lamps with current supplied at 50 Hz, 400 Hz and modulated between 15 and 35 kHz
353
Test results from recent 1.8-M SSC model dipoles
354
Test results from the 200 kA SMES/ETM conductor
355
Test results from the AN/APY-6 SAR/GMTI surveillance, tracking and targeting radar
356
Test results from the completed production run of superconducting corrector magnets for RHIC
357
Test results from the LLNL 250 GHz CARM experiment
358
Test results from the LQXB quadrupole production program at Fermilab for the LHC interaction regions
359
Test Results From the PF Conductor Insert Coil and Implications for the ITER PF System
360
Test results from the SMES proof of principle experiment
361
Test results from two 5m two-in-one superconducting magnets for the SSC
362
Test Results Obtained from a Brushless Unity-Power-Factor Induction Machine
363
Test Results Obtained from a Brushless Unity-Power-Factor Induction Machine
364
Test Results Obtained on the Low and High Energies Heavy Ion Test Facilities
365
Test results of "Tokamak-7" superconducting magnet system (SMS) sections
366
Test results of 14 kVA superconducting transformer with Bi-2223/Ag windings
367
Test Results of 15 T
Quadrupole Magnet HQ01 with a 120 mm Bore for the LHC Luminosity Upgrade
368
Test results of 2-kWh flywheel using passive PM and HTS bearings
369
Test results of 310 GHz hologram compact antenna test range
370
Test results of 50 MVA superconducting generator
371
Test Results of 52/68 kA Trial HTS Current Leads for ITER
372
Test Results of 60 kVA Current Limiting Transformer With Full Recovery Under Load
373
Test Results of a
Cable-in-Conduit Conductor With Variable Pitch Sequence
374
Test Results of a
Nb
3
Sn
Wind/React “Stress-Managed” Block Dipole
375
Test results of a 1.5 kA HTS current lead for /spl mu/SMES
376
Test results of a 10 kA current lead using Ag/Au cladded Bi-2212 tubes [for ITER-FEAT coils]
377
Test results of a 10 kA current lead using Ag/Au stabilized Bi-2223 tapes
378
Test Results of a 100 kA NbTi CICC
379
Test results of a 130 W AC module; a modular solar AC power station
380
Test Results of a 2 Tesla Superconducting Transmission Line Magnet Obtained With 102 Sensors Array of Hall Station
381
Test results of a 20 kA current lead using Ag/Au stabilized Bi-2223 tapes
382
Test results of a 30 m high-Tc superconducting power cable
383
Test Results of a 30 m HTS Cable for Yokohama Project
384
Test results of a 94 GHz, 10 kW gyrotron and a 60 GHz, 200 kW gyrotron
385
Test results of a cable-in-conduit superconductor for the WENDELSTEIN 7-X stellarator
386
Test results of a CdZnTe pixel detector read out by RENA-2 IC
387
Test results of a chip for the separation of mixed and filtered signals
388
Test results of a combined distributed ion pump/non-evaporable getter pump design developed as a proposed alternative pumping system for the PEP-II asymmetric B-factory collider
389
Test Results of a Compact Disk-Type Motor/Generator Unit With Superconducting Bearings for Flywheel Energy Storage Systems With Ultra-Low Idling Losses
390
Test results of a compact smooth-walled spline-profile horn at 30-38 GHz for radio astronomy application
391
Test Results of a Compact Superconducting Flywheel Energy Storage With Disk-Type, Permanent Magnet Motor/Generator Unit
392
Test results of a concentrating photovoltaic module using Kohler integration optics for flux homogenization
393
Test results of a demonstration HTS magnet for minesweeping
394
Test results of a fast beam chopper with MA cores
395
Test Results of a High Capacity Wayside Energy Storage System Using Ni-MH Batteries for DC Electric Railway at New York City Transit
396
Test results of a HTS Reciprocating Magnetic Separator
397
Test Results of a Large Size, Forced Flow Nb
3
Sn Conductor, Based on a Design Alternative to the Cable-in-Conduit
398
Test Results of a Nb
3
Al/Nb
3
Sn Subscale Magnet for Accelerator Application
399
Test Results of a NbTi Wire for the ITER Poloidal Field Magnets: A Validation of the 2-Pinning Components Model
400
Test Results of a Planar Superconducting Undulator for the Advanced Photon Source
401
Test results of a precise, short range, RF navigational/positional system
402
Test results of a resistive SC-power switch of 40 MW switching power at a voltage of 47 kV
403
Test results of a single aperture 10 tesla dipole model magnet for the Large Hadron Collider
404
Test results of a single aperture dipole model magnet for LHC
405
Test Results of a Small Size CICC With Advanced
Strands
406
Test results of a space-time adaptive processing system for airborne early warning radar
407
Test results of a SRM made of layered block of heat-treated amorphous alloys
408
Test Results of a Superconducting Fault Current Limiter Using YBCO Coated Conductor
409
Test Results of a Superconducting FCL Using Bifilar Coil of BSCCO-2212
410
Test Results of a Superconducting Quadrupole Model Designed for Linear Accelerator Applications
411
Test results of a three phase HTS transformer with double pancake windings
412
Test results of a time-dispersed forward error control system
413
Test results of a variant-design LHC twin-aperture dipole magnet
414
Test Results Of A Very High Field, explosive magnetic flux compression generator
415
Test Results of AC Superconducting Cables
416
Test Results of AC Superconducting Cables
417
Test results of an apparatus for calorimetric measurement of AC losses in superconductors
418
Test results of an automatic calibration system for AC-DC thermal voltage converters and AC voltage sources
419
Test results of an experimental autonomous aircraft landing system utilizing a 94 GHz FM-CW imaging radar
420
Test results of an experimental holographic acoustic imaging system
421
Test results of an inner-cooled generator
422
Test results of an ITER relevant FPGA when irradiated with neutrons
423
Test results of an RR-type micromechanical gyroscope
424
Test Results of an SRM Made From a Layered Block of Heat-Treated Amorphous Alloys
425
Test results of applicative 100 W Stirling engine
426
Test results of BNL built 40-mm aperture, 17-m-long SSC collider dipole magnets
427
Test Results of CCT1—A 2.4 T Canted-Cosine-Theta Dipole Magnet
428
Test Results of Central Magnetic Field and Field Uniformity of a High Temperature Superconducting Magnet With Gap
429
Test results of compensation for load fluctuation under a fuzzy control by a 1 kWh/1 MW SMES
430
Test results of computer-generated simulated driving profiles applied to near-term batteries
431
Test results of different silver/graphite contact materials in regard to applications in circuit breakers
432
Test results of F/A-18 autoland trials for aircraft carrier operations
433
Test results of full-scale HTS cable models and plans for a 36 kV, 2 kA
rms
utility demonstration
434
Test results of grounding methods on distribution transformers during maintenance of overhead distribution lines
435
Test results of HD1b, an upgraded 16 tesla Nb
3
Sn dipole magnet
436
Test Results of High Performance HTS Pancake Coils at 77 K
437
Test results of high ramp rate pulsed superconducting coil for the reacting plasma tokamak
438
Test results of high temperature superconductor current lead at 14.5 kA operation
439
Test results of high torque and high efficiency SRMs designed for 50kW Hybrid Electric Vehicle
440
Test Results of HTS Coils and an R&D Magnet for RIA
441
Test results of HTS dipole
442
Test Results of LARP
Quadrupole Magnets Using a Shell-Based Support Structure (TQS)
443
Test Results of LARP 3.6 m
Racetrack Coils Supported by Full-Length and Segmented Shell Structures
444
Test results of LHC interaction regions quadrupoles produced by Fermilab
445
Test results of long term operation of the superfluid-cooled cryostat for a 1 GHz NMR spectrometer
446
Test results of multi channel readout system for high performance scintillation imaging
447
Test results of Nb
3
Sn ribbons for the Princeton D coil test program
448
Test results of personal protective grounding on distribution line wood pole construction
449
Test results of post-ASST design Fermilab built 1.5 meter, SSC collider model dipole magnets
450
Test Results of Power System Control by Experimental SMES
451
Test results of pre-production prototype distributed ion pump design for the PEP-II asymmetric B-Factory collider
452
Test Results of Pressure Head Mitigation of Supercritical Helium Across Cold Circulators at KSTAR for the Justification of the ITER Central Solenoid Cooling Circuit Design
453
Test results of RD3c, a Nb
3
Sn common-coil racetrack dipole magnet
454
Test Results of Real-the Algorithms Executed on FDPP with Spacal Data
455
Test Results of RF ITER TF Conductors in the SULTAN Test Facility
456
Test results of SeCRETS, a stability experiment about segregated copper in CICC
457
Test results of shell-type Nb
3
Sn dipole coils
458
Test results of single-event effects conducted by the Jet Propulsion Laboratory
459
Test results of spare TRISTAN insertion quadrupole magnet with yoke added in superfluid helium
460
Test results of superconducting AC magnets for magnetic refrigeration experiment
461
Test Results of Superconducting Combined Function Magnets for the J-PARC Neutrino Beam Line
462
Test Results of Superconducting Combined Function Prototype Magnets for the J-PARC Neutrino Beam Line
463
Test Results of Superconducting Magnets for the J-PARC Neutrino Beam Line
464
Test results of the 5 kA/sub RMS/-50 kV/sub RMS/ HTS AC lead
465
Test Results of the 7 OHM, 2.5 MV, Laser Triggered PFL for the HYDRUS IVA
466
Test results of the 8.35 kA, 15 kV, 10 pps pulser for the Elettra kickers
467
Test results of the 805-MHz, 550 kW pulsed klystron for the spallation neutron source
468
Test Results of the AFS Hadron Calorimeter at the CERN ISR
469
Test results of the AGS booster low frequency RF system
470
Test results of the Atlas Marxed pulsed power system
471
Test results of the Doppler penetrometer seafloor sediment profiling system
472
Test results of the FER/ITER conductors in the FENIX test facility
473
Test Results of the First 3.7 m Long Nb3Sn Quadrupole by LARP and Future Plans
474
Test Results of the First US ITER TF Conductor in SULTAN
475
Test results of the g-2 superconducting solenoid magnet system
476
Test Results of the High Temperature Superconductor Prototype Current Leads for Wendelstein 7-X
477
Test results of the ITER PF insert conductor short sample in SULTAN
478
Test Results of the LARP HQ02b Magnet at 1.9 K
479
Test Results of the Model Coil for the 40 T Hybrid Magnet Superconducting Outsert
480
Test results of the NavCore V GPS receiver engine
481
Test Results of the PEFP 3MeV RFQ Upgrade
482
Test results of the prototype combined sextupole-dipole corrector magnet for LHC
483
Test results of the Q1 quadrupoles for the CEBAF high resolution spectrometer
484
Test results of the readout electronics for nuclear applications (RENA) chip
485
Test results of the SeaKeepers ocean sensor module on remote platforms
486
Test results of the small model coil for a /spl mu/smes device
487
Test results of the small model coil for a small-sized superconducting magnetic energy storage device
488
Test results of the SSC log-ratio beam position monitor electronics
489
Test Results of the ST1 GPS Time Transfer Receiver
490
Test Results of the Thin Superconducting Solenoid for the CMD-3 Detector
491
Test Results of the Third Japanese SULTAN Sample
492
Test results of the third LHC main quadrupole magnet prototype at CEA/Saclay
493
Test results of the toroidal model pancake for ITER/FER toroidal field coils
494
Test results of the US-LCT pool-boiling coils in the International Fusion Superconducting Magnet Test Facility (IFSMTF)
495
Test results of the world´s largest four-pole generators with water-cooled stator and rotor windings
496
Test results of three excitation systems for generators suffering continuous voltage flicker disturbance
497
Test Results of Three Poloidal Field Superconducting Samples in SULTAN
498
Test results of total ionizing dose conducted at the Jet Propulsion Laboratory [bipolar and CMOS ICs]
499
Test Results of Two European ITER TF Conductor Samples in SULTAN
500
Test Results of Two ITER TF Conductor Short Samples Using High Current Density Nb
Sn Strands
501
Test results of various CMOS image sensor pixels
502
Test Results on
MgB
2
Windings for AC Applications
503
Test results on 10 T LHC superconducting one metre long dipole models
504
Test results on 3 GHz structures for a superconducting linear collider
505
Test Results on 500 kVA-Class
MgB
2
-Based Fault Current Limiter Prototypes
506
Test results on a free-cylinder Stirling engine
507
Test Results On A Kilowatt-scale Sodium Heat Engine
508
Test Results on a Low Loss Amorphous Iron Induction Motor
509
Test Results on a Low Loss Amorphous Iron Induction Motor
510
Test results on a super-high-speed amorphous-iron reluctance motor
511
Test results on a thermo-syphon concept to high-power cool desktop computers and servers
512
Test results on an experimental crosstie random access memory (CRAM)
513
Test results on an MNOS memory array
514
Test results on capacitor commutation charging type of resonant power supply for synchrotron ring magnets
515
Test results on DC injection phenomenon of grid connected PV system at Rokko test center
516
Test results on double sided readout silicon strip detectors
517
Test Results on Experimental SMES System With Normal Conducting Shielding Coils
518
Test results on heavily irradiated silicon detectors for the CMS experiment at LHC
519
Test results on heavily irradiated silicon detectors for the CMS experiment at LHC
520
Test results on the 9-cell 1.3 GHz superconducting RF cavities for the TESLA test facility linac
521
Test results on the first 13 kA prototype HTS leads for the LHC
522
Test results on the long models and full scale prototypes of the second generation LHC arc dipoles
523
Test Results on the New TSZ Calibration Method
524
Test results on the performance of suspension insulators in service
525
Test Results on the Performance of Suspension Insulators in Service
526
Test results over extended environments for Litton´s inertial navigation grade interferometric fiber optic gyro
527
Test Results -Test Method For Determining The Protective Performance Of A Shield Attached On Live Line Tools Or On Racking Rods for Electric Arc Hazards
528
Test Results with an Experimental Direction-Finding System
529
Test results with the direct flux linkage control of synchronous motors
530
Test reuse in the spreadsheet paradigm
531
Test rig for high speed electromechanical flywheels in Sub Saharan Africa
532
Test rig for induction motor quasi-static electromechanical characteristic determination
533
Test Roles in Diagnosis and Silicon Debug
534
Test sample size determination for biometric systems based on confidence elasticity
535
Test Scenario Generation for Reliability Tactics from UML Sequence Diagram
536
Test scenario generation from a structured requirements specification
537
Test scenario modeling: Modeling test scenarios diagrammatically using specification based testing techniques
538
Test scenario selection for concurrency testing from UML models
539
Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands
540
Test Schedules for VLSI Circuits Having Built-In Test Hardware
541
Test scheduling and control for VLSI built-in self-test
542
Test scheduling and controller synthesis in the CADDY-system
543
Test scheduling and scan-chain division under power constraint
544
Test scheduling and test access architecture optimization for system-on-chip
545
Test scheduling for built-in self-tested embedded SRAMs with data retention faults
546
Test scheduling for core-based SOCs
547
Test scheduling for core-based systems
548
Test scheduling for core-based systems using mixed-integer linear programming
549
Test scheduling for embedded systems
550
Test scheduling for high performance VLSI system implementations
551
Test Scheduling for Memory Cores with Built-In Self-Repair
552
Test scheduling for minimal energy consumption under power constraints
553
Test scheduling for modular SOCs in an abort-on-fail environment
554
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands
555
Test scheduling for network-on-chip with BIST and precedence constraints
556
Test Scheduling for SOC under Power Constraints
557
Test scheduling for system-on-a-chip using test resource grouping
558
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
559
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
560
Test scheduling in high performance VLSI system implementations
561
TEST SCHEDULING IN TESTABLE VLSI CIRCUITS
562
Test scheduling of BISTed memory cores for SoC
563
Test scheduling of SOC IP interconnect for static and SI faults
564
Test Scheduling of SOC with Power Constraint Based on Particle Swarm Optimization Algorithm
565
Test scheduling using Ant Colony Optimization for 3D integrated circuits
566
Test scheduling using test subsession partitioning
567
Test scheduling with loop folding and its application to test configurations with accumulators
568
Test scheduling with power-time tradeoff and hot-spot avoidance using MILP
569
Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking
570
Test scheme for switched-capacitor circuits by digital analyses
571
Test scheme of SOC test with multi-constrained to reduce test time
572
Test Scheme Setup for the PEFP 20 MeV DTL
573
Test schemes for master station of distribution automation systems
574
Test script execution and effective result analysis in hybrid test automation framework
575
Test Script Generation Based on Design Documents for Web Application Testing
576
Test scripting — An alternative approach to realtime instrument control
577
Test Selection and Coverage Based on CTM and Metric Spaces
578
Test selection based on communicating nondeterministic finite-state machines using a generalized Wp-method
579
Test selection based on finite state models
580
Test selection based on high level fault simulation for mixed-signal systems
581
Test selection based on implementation specification
582
Test Selection based on Improved Binary Particle Swarm Optimization
583
Test Selection Criteria for Modal Specifications of Reactive Systems
584
Test Selection for Data-Flow Reactive Systems Based on Observations
585
Test selection for result inspection via mining predicate rules
586
Test selection from UML Statecharts
587
Test selection of complex electronic system based on small world network and improved particle swarm optimization
588
Test Selection Policies for Faster Incremental Fault Detection
589
Test Selection Prioritization Strategy
590
Test Selection with Equivalence Class Partitioning
591
Test selections and coverages
592
Test sequence algorithms and formal languages
593
Test sequence compaction by reduced scan shift and retiming
594
Test sequence compaction for sequential circuits with reset states
595
Test sequence generating method of Cooperative Vehicle Infrastructure System based on support index
596
Test sequence generation and optimization method based on Cooperative Vehicle Infrastructure System simulation
597
Test sequence generation for protocol conformance testing
598
Test sequence generation for realistic faults in CMOS ICs based on standard cell library
599
Test Sequence Generation from Classification Trees
600
Test sequence generation from classification trees
601
Test Sequence Generation from Combining Property Modeling and Program Slicing
602
Test Sequence Generation from Communicating UML State Charts: An Industrial Application of Symbolic Transition Systems
603
Test sequence generation from formal specifications of distributed programs
604
Test Sequence Generation from UML Sequence Diagrams
605
Test sequence generation methods for protocol conformance testing
606
Test sequence generation of Random Single Input Change based on counter
607
Test sequences as plans: an experiment in using an AI planner to generate system tests
608
Test sequences generation from LUSTRE descriptions: GATEL
609
Test sequences to achieve high defect coverage for synchronous sequential circuits
610
Test sequencing algorithms with unreliable tests
611
Test Sequencing in Complex Manufacturing Systems
612
Test sequencing in modular systems
613
Test sequencing problems arising in test planning and design for testability
614
Test Sequencing Strategy with Imperfect Test
615
Test session oriented built-in self-testable data path synthesis
616
Test set compaction algorithms for combinational circuits
617
Test set compaction algorithms for combinational circuits
618
Test set compaction for combinational circuits
619
Test set compaction for combinational circuits
620
Test set compaction procedure for combinational circuits based on decomposition tree
621
Test set customization for improved fault diagnosis without sacrificing coverage
622
Test Set Development for Cache Memory in Modern Microprocessors
623
Test set embedding based on width compression for mixed-mode BIST
624
Test set embedding for deterministic BIST using a reconfigurable interconnection network
625
Test set embedding in a built-in self-test environment
626
Test set embedding into accumulator-generated sequences targeting hard-to-detect faults
627
Test set embedding into hardware generated sequences using an embedding algorithm
628
Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching
629
Test set embedding into low-power sequences based on a traveling salesman problem formulation
630
Test set encoding for efficient sequential circuit testing
631
Test Set Enrichment using a Probabilistic Fault Model and the Theory of Output Deviations
632
Test set for the measurement of IMDS at 900 MHz
633
Test Set for the Measurement of Transmitter Stability Parameters
634
Test set generation almost for free using a run-time FPGA reconfiguration technique
635
Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques
636
Test Set Optimization Based on Intelligent Hybrid Algorithm
637
Test set partitioning and dynamic fault dictionaries for sequential circuits
638
Test set problem for multilevel systems
639
Test Set Reordering Using the Gate Exhaustive Test Metric
640
Test set selection for structural faults in analog IC´s
641
Test set size minimization and fault detection effectiveness: a case study in a space application
642
Test Set Stripping Limiting the Maximum Number of Specified Bits
643
Test Set Validation for Home Electrical Signal Disaggregation
644
Test sets and reject rates: all fault coverages are not created equal
645
Test Sets for Combinational Logic—The Edge-Tracing Approach
646
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits
647
Test setup and spurious replicas identification in time-quantized pseudorandom sampling-based ADC in SDR multistandard receiver
648
Test setup for accelerated test of high power IGBT modules with online monitoring of V
ce
and V
f
voltage during converter operation
649
Test setup for anechoic room based MIMO OTA testing of LTE terminals
650
Test setup for error vector magnitude measurement on WLAN transceivers
651
Test setup for long term reliability investigation of Silicon Carbide MOSFETs
652
Test setup for multi-finger gripper control based on robot operating system (ROS)
653
Test setup for optical burst-mode receivers
654
Test setup for radio emission from a load-wire connecting LEDs
655
Test Setup for Supporting Human Implantation of Intracortical Visual Prosthesis Device
656
Test setup simulation - a high-performance VHDL-based virtual test solution meeting industrial requirements
657
Test Signal Design and Analysis for Multi-Channel Identification
658
Test Signal Development and Analysis for OFDM Systems RF Front-End Parameter Extraction
659
Test signal generation for the calibration of analog front-end circuits in biopotential measurement applications
660
Test signal reduction in radiated EMI measurements
661
Test signals and automatic measurement methods for HDMAC signal
662
Test signals for music reproduction systems
663
Test Simulation An Effective Approach to Reduce Development Cost of Mobile Phone
664
Test Simulation System Design Based on Java Language
665
Test site aided new IC product introduction
666
Test site and methodologies for testing and comparing energy storage systems for UPS, load management and power quality applications
667
Test site for the analysis of subsoil GPR signal propagation
668
Test site image analysis for SAR radiometric performance determination using a statistical method
669
Test Site Validation above 1GHz
670
Test Sites and Testing of 3-Sun Mirror Modules
671
Test slice difference technique for low power encoding
672
Test socket chip for measuring dark currents in IR FPA
673
Test software at Texas Instruments: what SEI level is appropriate?
674
Test software design techniques for reuse and portability
675
Test software evaluation using data logging [missile testing]
676
Test software for system of electrochemical LIA material research
677
Test Software Generation Productivity and Code Quality Improvement by applying Software Engineering Techniques
678
Test solution for data retention faults in low-power SRAMs
679
Test solution for OTA based analog circuits
680
Test solution selection using multiple-objective decision models and analyses
681
Test solutions for nanoscale Systems-on-Chip: Algorithms, methods and test infrastructure
682
Test SPC: a process to improve test system integrity
683
Test Specimen Shape Considerations for the Measurement of Rotational Core Losses
684
Test specimen shape considerations for the measurement of rotational core losses
685
Test speed dependency of peel strength of ACF joints
686
Test SQL injection vulnerabilities in web applications based on structure matching
687
Test SRAMs for characterizing alpha particle tracks in CMOS/bulk memories
688
Test stand for high voltage insulator partial discharge testing with ultra short X-ray pulses
689
Test stand for linear induction accelerator optimization
690
Test stand for shock compression of gas-impregnated solids
691
Test stand for testing contacts of switches in a fixed household electrical installations
692
Test stand for the Silicon Vertex Detector of the Collider Detector Facility
693
Test stand for the Silicon Vertex Detector of the Collider Detector Facility
694
Test standards (with focus on IEEE1149.1)
695
Test stands for the central drift chamber front end hybrid in the Stanford Linear Collider Detector
696
Test station configuration and health management
697
Test station controller replacement using commercial products
698
Test station for CCSDS based data handling systems of mini satellites
699
Test station for magnetization measurements on large quantities of superconducting strands
700
Test station for the LHCb muon front-end boards (November 2005)
701
Test station workcell controller and resource relationship design
702
Test statistics for synthetic aperture radar coherent change detection
703
Test strategies for a 3-D stack multichip module space flight computer
704
Test strategies for a 40 Gbps framer SoC
705
Test strategies for a family of complex MCMs
706
Test strategies for adaptive equalizers
707
Test strategies for BIST at the algorithmic and register-transfer levels
708
Test strategies for cost-sensitive decision trees
709
Test strategies for fine pitch wafer level packaged devices
710
Test Strategies for Low Power Devices
711
Test Strategies for Mass Production of Lenses in High Concentration PV systems
712
Test Strategies for minimizing the overall cost of test in moving from “cost based/government furnished equipment” to “firm fixed price” contracts
713
Test strategies for multi-chip modules based on economics considerations
714
Test strategies for nanometer technologies
715
Test strategies for power supplies
716
Test Strategies for Reliable Runtime Reconfigurable Architectures
717
Test strategies for SoC quality
718
Test strategies on functionally partitioned module-based programmable architecture for base-band processing
719
Test Strategies on Non Volatile Memories Electrical Wafer Sort on NAND, NOR Flash and Phase Change Memories
720
Test Strategies Using Operational Profiles Based on Decision Tables
721
Test strategy component of an open architecture for electronics design and support tools
722
Test strategy cost model innovations
723
Test strategy for DSL broadband IP access services
724
Test Strategy for Microprocessers
725
Test Strategy for RF & Microwave Semiconductor Devices for Wireless Communications Market
726
Test strategy for the PowerPC 750 microprocessor
727
Test Strategy For The Signal Processor KISS16
728
Test strategy planning environments for VLSI systems
729
Test strategy planning method for complex integrated circuits
730
Test strategy selection for multi-chip systems
731
Test strategy sensitivity to defect parameters
732
Test strategy sensitivity to floating gate fault parameter
733
Test stream generation framework for video quality assessment methodology evaluation
734
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits
735
Test strip—Research on rapid determination of Chromium in water by photoelectric detecto
736
Test structure and analysis for accurate RF-characterization of tungsten through silicon via (TSV) grounding devices
737
Test Structure and e-Beam Inspection Methodology for In-line Detection of (Non-visual) Missing Spacer Defects
738
Test structure and experimental analysis of bipolar hot-carrier degradation including stress field effect
739
Test structure and method for capacitance extraction in multi-conductor systems
740
Test structure and method for the experimental investigation of internal voltage amplification and surface potential of ferroelectric MOSFETs
741
Test structure and methodology for experimental extraction of threshold voltage shifts due to quantum mechanical effects in MOS inversion layers
742
Test structure and simplified distribution model for identification of base resistance components in self-aligned polysilicon base electrode bipolar transistors
743
Test Structure and Testing of the Microsoft XBOX 360/sup TM/ Processor High Speed Front Side Bus
744
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC´s
745
Test structure data classification using a directed graph approach
746
Test structure definition for dummy metal filling strategy dedicated to advanced integrated RF inductors
747
Test structure design considerations for RF-CV measurements on leaky dielectrics
748
Test structure design considerations for RF-CV measurements on leaky dielectrics
749
Test structure design for a fast and simple evaluation of carrier mobilities in highly injected regions
750
Test structure design for measuring electron and hole mobilities at very high injection levels
751
Test Structure Design for Precise Understanding of Cu/Low-k Dielectric Reliability
752
Test structure design for the evaluation of carrier-carrier scattering effect on hole and electron mobilities
753
Test Structure Design, Extraction, and Impact Study of FEOL Capacitance Parameters in Advanced 45nm Technology
754
Test structure designed for vias in multi-layer package substrate
755
Test structure failed node localization and analysis from die backside
756
Test structure for characterising low voltage coplanar EWOD system
757
Test Structure for Characterization of Low-Frequency Noise in CMOS Technologies
758
Test structure for characterization of polycrystalline silicon as a diffusion source for advanced devices
759
Test structure for characterizing capacitance matrix of multi-layer interconnections in VLSI
760
Test Structure for Characterizing Low Voltage Coplanar EWOD System
761
Test structure for characterizing metal thickness in damascene CMP technology
762
Test structure for crosstalk characterisation
763
Test structure for determining boron diffusion coefficient in tungsten silicide
764
Test structure for determining the charge distribution in the oxide of MOS structure
765
Test structure for direct extraction of capacitance matrix in VLSI
766
Test structure for electrical characterization of copper nanowire anisotropic conductive film (NW-ACF) for 3D stacking applications
767
Test structure for evaluation of 1/f noise in CMOS technologies
768
Test structure for fixing OPC of 200 nm pitch via chain using inner and outer dummy via array
769
Test Structure for High Voltage LD-MOSFET Device Mismatch Investigations
770
Test Structure for High-Voltage LD-MOSFET Mismatch Characterization in 0.35 um HV-CMOS Technology
771
Test structure for I
C
(V
BE
) parameter determination of low voltage applications
772
Test structure for investigating activated doping concentrations in polycrystalline silicon
773
Test structure for measurement of conductive film thickness
774
Test structure for measurement of ion stopping power
775
Test structure for mismatch characterization of MOS transistors in subthreshold regime
776
Test structure for performance evaluation of 3 dimensional FinFETs
777
Test structure for precise statistical characteristics measurement of MOSFETs
778
Test Structure for Process and Product Evaluation
779
Test structure for the detection, localization and identification of short circuits with a high speed digital tester
780
Test structure for the in-plane locations of project features with nanometer-level accuracy traceable to a coordinate measurement system
781
Test structure for thermal monitoring
782
Test structure for universal estimation of MOSFET substrate effects at gigahertz frequencies
783
Test structure generation to quantify filling impact
784
Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution
785
Test Structure Methodology of IC Package Material Characterization
786
Test structure metrology of homogeneous contamination
787
Test Structure on SCR Device in Waffle Layout for RF ESD Protection
788
Test structure to evaluate the impact of neighboring features on stress of metal interconnects
789
Test Structure to Extract Circuit Models of Nanostructures Operating at High Frequencies
790
Test structure to investigate the series resistance components of source/drain structure
791
Test structure to measure the gate-drain coupling capacitor using accelerated techniques
792
Test structure verification of logical BIST: problems and solutions
793
Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density
794
Test structures and a measurement system for characterising the lifetime of EWOD devices
795
Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability
796
Test structures and DRIE topography for bulk silicon MEMS devices
797
Test structures and finite element models for chip stress and plastic package reliability
798
Test structures and measurement of gate sidewall junction capacitance in MOSFETs
799
Test structures and measurement techniques for the characterization of the dynamic behaviour of CMOS transistors on wafer in the GHz range
800
Test structures and test methodology for developing high voltage ESD protection
801
Test structures applied to the rapid prototyping of sensors
802
Test structures based VLSIC yield ramp maximization
803
Test structures for a MEMS SiO
x
/metal process
804
Test Structures for Accurate UHF C-V Measurements of Nano-Scale CMOSFETs with HfSiON and TiN Metal Gate
805
Test structures for analysis and parameter extraction of secondary photon-induced leakage currents in CMOS DRAM technology
806
Test structures for analyzing proton radiation effects in bipolar technologies
807
Test structures for analyzing radiation effects in bipolar technologies
808
Test structures for analyzing the mechanisms of wafer chemical contaminant removal
809
Test structures for automated contactless inline wafer inspection
810
Test structures for CD and overlay metrology on alternating aperture phase-shifting masks
811
Test structures for characterising a damascene CMP interconnect process
812
Test structures for characterising the integration of EWOD and SAW technologies for microfluidics
813
Test structures for characterization of electrooptic waveguide modulators in lithium niobate
814
Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design
815
Test structures for characterization of through silicon vias
816
Test Structures for Characterization of Through-Silicon Vias
817
Test Structures for Characterizing the Integration of EWOD and SAW Technologies for Microfluidics
818
Test structures for continuous determination of electrical parameters of substrate material up to 79 GHz
819
Test structures for determining design rules for microelectromechanical-based sensors and actuators
820
Test structures for electrical evaluation of high aspect ratio TSV arrays fabricated using planarised sacrificial photoresist
821
Test structures for electromigration evaluation in submicron technology
822
Test structures for evaluating strong phase shift lithography
823
Test structures for extraction of MOSFET capacitances
824
Test structures for HF characterization of fully differential building blocks
825
Test structures for hillock growth, via filling and for measuring the quality of thin films
826
Test structures for interdie variations monitoring in presence of statistical random variability
827
Test structures for investigation of metal coverage effects on MOSFET matching
828
Test structures for ISFET chemical sensors
829
Test structures for MCM-D technology characterization
830
Test structures for MCM-D technology characterization
831
Test structures for propagation delay measurements on high-speed integrated circuits
832
Test structures for quantum efficiency characterization for silicon image sensors
833
Test structures for rapid prototyping of gas and pressure sensors
834
Test structures for referencing electrical linewidth measurements to silicon lattice parameters using HRTEM
835
Test structures for referencing electrical linewidth measurements to silicon lattice parameters using HRTEM
836
Test structures for study of electron transport in nickel silicide features with line widths between 40 nm and 160 nm
837
Test structures for the characterisation of MEMS and CMOS integration technology
838
Test structures for the characterization of deep trench isolation [The following paper has been withdrawn by the authors]
839
Test Structures for the Characterization of MEMS and CMOS Integration Technology
840
Test structures for the electrical characterisation of platinum deposited by focused ion beam
841
Test structures for the evaluation of 3D chip interconnection schemes
842
Test structures for the evaluation of air-bridge interconnection in GaAs IC´s fabrication process
843
Test structures for the evaluation of Si substrates
844
Test structures for the wafer mapping and correlation of electrical, mechanical and high frequency magnetic properties of electroplated ferromagnetic alloy films
845
Test structures on MCM active substrate: is it worthwhile?
846
Test structures to characterise a novel circuit fabrication technique that uses offset lithography
847
Test structures to investigate thin insulator dielectric wearout and breakdown
848
Test structures to measure the heat capacity of CMOS layer sandwiches
849
Test structures to measure the heat capacity of CMOS layer sandwiches
850
Test structures to measure the Seebeck coefficient of CMOS IC polysilicon
851
Test structures to measure the Seebeck coefficient of CMOS IC polysilicon
852
Test structures to quantify contact placement-impacted drain current variations
853
Test structures to verify ESD robustness of on-glass devices in LTPS technology
854
Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement
855
Test Study and Contrast Analysis about Cold-formed Thin-wall Steel Joints
856
Test study for bi-directional thrust bearing
857
Test study of infection of rust damnification to vibration frequency for leaf of propeller
858
Test study of mechanical properties of reinforced loess
859
Test study of mechanism on the reaction of sodium hydroxide with silica from corn straw ash
860
Test study of performance of electronic scanivalve system
861
Test Study on Corona Onset Voltage of UHV Transmission Lines Based on UV Detection
862
Test study on domestic wastewater treatment by Coagulate-MBR
863
Test study on high strength high-neck forging flange of UHV steel tube transmission towers
864
Test study on size effect of flexural capacity of RC simple beams
865
Test study on size effect of short-term stiffness at using stage of flexural members
866
Test Study on Speed-dynamic Characteristic of reinforced roadbed at bridge approach
867
Test study on strengthening RC flexural members with grouting material
868
Test study on the seismic behavior of the cavity wall reinforced
869
Test study on water saving and environmental effects of rain-catching and controlled irrigation of rice
870
Test suite consistency verification
871
Test suite design for code generation tools
872
Test Suite for the LHCb Muon Chambers Quality Control
873
Test suite generation methods for concurrent systems based on coloured Petri nets
874
Test Suite generation using Memetic algorithm on adaptive local search
875
Test suite optimization using fuzzy logic
876
Test suite prioritisation using trace events technique
877
Test Suite Prioritization by Switching Cost
878
Test Suite Quality Assessment Using Model Inference Techniques
879
Test suite reduction analysis with enhanced tie-breaking techniques
880
Test Suite Reduction by Combinatorial-Based Coverage of Event Sequences
881
Test suite reduction for fault detection and localization: A combined approach
882
Test suite reduction for mutation testing based on formal concept analysis
883
Test Suite Reduction Using Weighted Set Covering Techniques
884
Test suite reduction with selective redundancy
885
Test suite selection based on traceability annotations
886
Test suites for benchmarks of static analysis tools
887
Test support processors for enhanced testability of high performance circuits
888
Test synthesis for datapaths using datapath-controller functions
889
Test synthesis for DC test and maximal diagnosis of switched-capacitor circuits
890
Test synthesis for DC test of switched-capacitors circuits
891
Test synthesis for mixed-signal SOC paths
892
Test Synthesis from UML Models of Distributed Software
893
Test synthesis in the behavioral domain
894
Test synthesis in the microprocessor product development cycle
895
Test synthesis of systems-on-a-chip
896
Test synthesis with alternative graphs
897
Test synthesis: an innovative approach to analog and system testability analysis using state dependent flow diagrams
898
Test synthesis: from wishful thinking to reality
899
Test synthesis-cutting the Gordian Knot
900
Test system consolidation
901
Test System Design of Lithium Battery Based on Fuzzy Self-Tuning PID Control
902
Test system for Charge Collection Efficiency measurement (SYCOC) for neutron irradiated silicon sensors
903
Test system for clinical force platforms
904
Test system for comprehensive evaluation of infrared-guided missiles
905
Test system for defect detection in construction materials with ultrasonic waves by support vector machine and neural network
906
Test system for device drivers of embedded systems
907
Test system for electric motors with integrated control unit
908
Test system for measurement of noise and coefficient of friction as a screen for potential lubricants in sliding electrical contacts
909
Test system for mobile field-strength recording
910
Test system for studies about devices´ behaviour at low temperature
911
Test system for the vehicles ESP control performances on the horizontal pendulum restriction vehicle system
912
Test System Impact on System Availability
913
Test system middleware - a foundation toolkit
914
Test system of 100GHz photodetector time response at NIM
915
Test system of a small wind turbine under laboratory conditions
916
Test system of external properties in magnetically controlled shape memory alloy of using labview
917
Test system of the time-over-threshold based chip optimized for linear transfer characteristics and low power for particle tracking applications
918
Test system requirements for modelling future power systems
919
Test system to determine the propagation and service area of cellular radio base stations
920
Test systems and mathematical models for transmission network expansion planning
921
Test systems for automotive radar
922
Test systems for dynamic stability studies in electric power system
923
Test systems for Economic Analysis — An introduction
924
Test systems for harmonics modeling and simulation
925
Test technique for passive inter-modulation distortion
926
Test Techniques
927
Test Techniques and Trade-offs for Embedded Cores and Systems
928
Test Techniques for Transient Radiation Effects
929
Test technology 20 years and beyond
930
Test Technology and Debouncing Circuit Design of Digitally Controlled Potentiometer
931
Test Technology Educational Progam (TTEP) Tutorials
932
Test Technology Educational Program (TTEP) 2008 Full-Day Tutorial
933
Test Technology Educational Program (TTEP) Tutorial 1
934
Test Technology Educational Program (TTEP) Tutorial 2
935
Test Technology Educational Program (TTEP) tutorials
936
Test Technology Educational Program (TTEP) Tutorials
937
Test Technology Educational Program (TTEP) Tutorials
938
Test Technology Educational Program (TTEP) Tutorials
939
Test technology educational program TTEP 2004 overview of tutorials of VTS 2004
940
Test technology educational program TTEP 2004 overview of tutorials of VTS 2004
941
Test technology educational program: Overview of tutorials
942
Test technology for amplitude-phase coherence of multi-channel phase coherent signal
943
Test technology for frequency selective surface material in RF integration
944
Test Technology Newsletter
945
Test Technology Newsletter
946
Test Technology Newsletter
947
Test technology of inner wall of tube based on CCD
948
Test Technology TC Membership [advertisement]
949
Test Technology TC Newsletter
950
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951
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952
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953
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954
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956
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958
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960
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961
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962
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963
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964
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965
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966
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967
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968
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970
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971
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972
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973
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974
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975
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976
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977
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978
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979
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980
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981
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982
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983
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984
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985
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986
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987
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988
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989
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990
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991
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993
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994
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995
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996
Test Technology Technical Committee
997
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998
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999
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1000
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