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VLSI Architecture for a real-time LPC-based feature extractor
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VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter
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VLSI architecture for a reconfigurable Spectrally Efficient FDM baseband transmitter
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VLSI Architecture for an adaptive equalizer in ISDN line termination
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VLSI architecture for an advance DS/CDMA wireless communication receiver
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VLSI architecture for an area efficient Elliptic Curve Cryptographic processor for embedded systems
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VLSI architecture for an object change detector for visual sensors
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VLSI architecture for an Underwater Robot Vision System
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VLSI architecture for analog bidirectional pulse-coupled neural networks
10
VLSI architecture for block-matching motion estimation algorithm
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VLSI architecture for coherent 9/7 lifting based 2D-discrete wavelet transform
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VLSI architecture for datapath integration of arithmetic over GF(2 m) on digital signal processors
13
VLSI architecture for data-reduced steering matrix feedback in MIMO systems
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VLSI architecture for digital picture comparison
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VLSI architecture for digital-recurrence algorithms on divider
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VLSI architecture for discrete wavelet transform
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VLSI architecture for discrete wavelet transform based on B-spline factorization
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VLSI architecture for dynamic time-warp recognition of handwritten symbols
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VLSI Architecture for Encryption and Watermarking Units Towards the Making of a Secure Camera
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VLSI architecture for hand-written symbol recognition
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VLSI architecture for HDTV motion estimation based on block-matching algorithm
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VLSI architecture for HDTV sub-band coding using GQMFs´ filterbanks
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VLSI architecture for hierarchical 2D mesh representation for very low bit rate applications
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VLSI architecture for hierarchical mesh-based motion estimation
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VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT
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VLSI architecture for high-speed rank and median filtering
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VLSI architecture for HMM-based speech recognition systems and its verification platform
28
VLSI architecture for IEEE 802.5 token-ring LAN controller
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VLSI architecture for image transformation
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VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight
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VLSI architecture for lossless compression of medical images using the discrete wavelet transform
32
VLSI architecture for low power motion estimation using high data access reuse
33
VLSI Architecture for Low Power Turbo Decoder using Adaptive Sliding Window Algorithm
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VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding
35
VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition
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VLSI architecture for motion estimation using the block-matching algorithm
37
VLSI architecture for motion vector quantization
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VLSI architecture for MQ coder in JPEG2000
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VLSI architecture for multi-resolution three step search algorithm
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VLSI architecture for parallel concentration-contour approach
41
VLSI architecture for quadtree-based fractal image coding
42
VLSI architecture for Rayleigh and Rician fading generators
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VLSI architecture for real time fire detection
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VLSI architecture for real-time fractal video encoding
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VLSI Architecture for Real-Time HD1080p View Synthesis Engine
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VLSI architecture for repetitive waveform measurement with zero overhead averaging
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VLSI architecture for SAR data compression
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VLSI Architecture for Separable Mellin Transform
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VLSI Architecture for signal processing with alternate low-level primitive structures (ALPS)
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VLSI architecture for significance map coding of embedded zerotree wavelet coefficients
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VLSI architecture for size-orientation-invariant pattern recognition
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VLSI architecture for soft-output tuple search sphere decoding
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VLSI Architecture for solving covariance eigen system
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VLSI architecture for sparse matrix multiplication
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VLSI Architecture for Spread Spectrum Image Watermarking in Walsh-Hadamard Transform Domain Using Binary Watermark
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VLSI Architecture for Spread Spectrum Image Watermarking Using Binary Watermark
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VLSI architecture for stack filters
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VLSI architecture for template matching
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VLSI architecture for the discrete wavelet transform
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VLSI architecture for the efficient computation of line spectral frequencies
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VLSI architecture for the embedded extraction of dominant points on object contours
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VLSI Architecture for the M Algorithm Suited for Detection and Source Coding Applications
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VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization
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VLSI architecture for very high resolution scalable video coding using the virtual zerotree
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VLSI architecture for video-assisted global positioning
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VLSI Architecture of 1.264 Block Size Decision based on Rate-Distortion Optimization
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VLSI Architecture of a 4Ã\x974 MIMO-OFDM Transceiver for over 1-Gbps Data Transmission
68
VLSI Architecture of a FIR Adaptive Filter
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VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel
70
VLSI architecture of a low complexity face detection algorithm for real-time video encoding
71
VLSI architecture of a MPEG-4 visual renderer
72
VLSI architecture of a real-time Wigner distribution processor for acoustic signals
73
VLSI architecture of a scalable matrix transposer
74
VLSI architecture of a wireless channel estimator using sequential Monte Carlo methods
75
VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera
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VLSI Architecture of Arithmetic Coder Used in SPIHT
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VLSI architecture of bit-serial quasicyclic encoders
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VLSI architecture of burst mode acceleration for 128-bit block ciphers
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Vlsi Architecture Of Cdma Rake Receiver With Low Hardware Complexity For Pcs
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VLSI architecture of centroid tracking algorithms for video tracker
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VLSI architecture of defect feature extraction based on wavelet packet in ultrasonic nondestructive test
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VLSI architecture of digital matched filter and prime interleaver for W-CDMA
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VLSI Architecture of DWT Based Watermark Encoder for Secure Still Digital Camera Design
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VLSI architecture of dynamically reconfigurable hardware-based cipher
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VLSI architecture of EBCOT Tier-2 encoder for JPEG2000
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VLSI architecture of EBCOT tier-2 encoder for JPEG2000
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VLSI architecture of exponential block for non-linear SVM classification
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VLSI architecture of extended in-place path metric update for Viterbi decoders
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VLSI architecture of forward and inverse quantization modules of H.264 for HD transmission
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VLSI architecture of HEVC intra prediction for 8K UHDTV applications
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VLSI architecture of leading eigenvector generation for on-chip principal component analysis spike sorting system
92
VLSI Architecture of Line-Based Lifting Wavelet Transform for Motion JPEG2000
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VLSI Architecture of List Sphere Decoder
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VLSI architecture of lossless ECG compression design based on fuzzy decision and optimisation method for wearable devices
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VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications
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VLSI architecture of multiplier-less DWT image processor
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VLSI architecture of NEO spike detection with noise shaping filter and feature extraction using informative samples
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VLSI architecture of Pairwise Linear SVM for facial expression recognition
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VLSI architecture of QMF for DWT integrated system
100
VLSI architecture of Rayleigh fading simulator based on IIR filter and polyphase interpolator
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VLSI architecture of signal processing chip set for 42-inch DC PDP HDTV receiver
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Vlsi Architecture Of Signal Processing Chip Set For 42-inch Dc Pdp Hdtv Receiver
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VLSI architecture of supplemental enhancement information module and modified quantization module for H.263+ video codec
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VLSI architecture of the blind carrier phase tracking with guaranteed global convergence
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VLSI architecture of the generalized multi delay frequency-domain algorithm for acoustic echo cancellation
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VLSI architecture of the reconfigurable computing engine for digital signal processing applications
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VLSI architecture of the soft-output sphere decoder for MIMO systems
108
VLSI Architecture of Video Post-Processing System for MPEG/H.26X
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VLSI architecture prototyping of pipelined IIR digital filter
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VLSI architecture: past, present, and future
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Vlsi Architectures And Implementation Of Predictive Tree-searched Vector Quantizes For Real-time Video Compression
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VLSI architectures for a high-speed tunable digital modulator/ demodulator/bandpass-filter chip set
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VLSI architectures for accurate motion and disparity estimation using full-search block-matching and edge preserving non-linear smoothing
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VLSI architectures for associative networks
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VLSI architectures for blind equalization based on fractional-order statistics
116
VLSI architectures for block matching algorithms
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VLSI architectures for block matching algorithms using systolic arrays
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VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2m)
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VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2m)
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VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
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VLSI architectures for computing the arithmetic Fourier transform
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VLSI architectures for computing X mod m
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VLSI architectures for convolver design using number theoretic transforms
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VLSI architectures for depth estimation using intensity gradient analysis
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VLSI architectures for digital image coding
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VLSI architectures for Digital Modulation Classification using Support Vector Machines
127
VLSI architectures for Dirichlet arithmetic
128
VLSI architectures for discrete wavelet transforms
129
VLSI architectures for distributed smart cameras
130
VLSI architectures for DSP applications: current trends
131
VLSI architectures for dynamic time warping using systolic arrays
132
VLSI architectures for field programmable gate arrays: a case study
133
VLSI architectures for Givens Rotation based RLS lattice ladder FIR filter algorithms using circular buffer technique
134
VLSI architectures for hierarchical block matching
135
VLSI architectures for hierarchical block matching algorithms
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VLSI architectures for high-speed and flexible two-dimensional digital filters
137
VLSI architectures for high-speed MAP decoders
138
VLSI architectures for high-speed range estimation
139
VLSI architectures for image processing and address mapping
140
VLSI architectures for image transformation
141
VLSI architectures for iterative decoders in magnetic recording channels
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VLSI Architectures for JPEG 2000 EBCOT
143
VLSI architectures for lattice structure based orthonormal discrete wavelet transforms
144
VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax
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VLSI Architectures for Lifting-Based Discrete Wavelet Packet Transform
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VLSI architectures for median filtering with linear complexity
147
VLSI architectures for metric normalization in the Viterbi algorithm
148
VLSI architectures for MPEG
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VLSI Architectures for Multidimensional Fourier Transform Processing
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VLSI architectures for multidimensional transforms
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VLSI architectures for multimedia
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VLSI architectures for multiplication in GF(2m) for application tailored digital signal processors
153
VLSI architectures for neural networks
154
VLSI architectures for object recognition
155
VLSI architectures for polygon recognition
156
VLSI architectures for programmable sorting of analog quantities with multiple-chip support
157
VLSI architectures for real-time moving image resampling
158
VLSI architectures for recursive and multiple-window order statistic filtering
159
VLSI architectures for recursive median filters
160
VLSI architectures for SISO-APP decoders
161
VLSI Architectures for Soft-Decision Decoding of Reed–Solomon Codes
162
VLSI architectures for soft-decision decoding of Reed-Solomon codes
163
VLSI architectures for stereoscopic video disparity matching and object extraction
164
VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers
165
VLSI architectures for the 4-tap and 6-tap 2-D Daubechies wavelet filters using pipelined direct mapping method
166
VLSI architectures for the discrete wavelet transform
167
VLSI Architectures for the Finite Impulse Response Filter
168
VLSI architectures for the full-search blockmatching algorithm
169
VLSI architectures for the implementation of the Wigner distribution
170
VLSI architectures for the MAP algorithm
171
VLSI architectures for turbo codes
172
VLSI Architectures for Turbo Decoding Message Passing Using Min-Sum for Rate-Compatible Array LDPC Codes
173
VLSI architectures for video compression
174
VLSI architectures for video compression-a survey
175
VLSI architectures for video signal processing
176
VLSI architectures for Viterbi decoding
177
VLSI architectures for weighted order statistic (WOS) filters
178
VLSI architectures of divider for finite field GF(2m)
179
VLSI architectures of domain adaptive fuzzy logic system
180
VLSI architectures of perceptual based video watermarking for real-time copyright protection
181
VLSI architectures of sparse distributed memory
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VLSI architectures of two-dimensional filters for HDTV coding
183
VLSI Architecuture for Neural Network Based Image Compression
184
VLSI area estimation tolerances-shape function generation vs. floorplanning
185
VLSI arithmetic with current mode multiple valued logic
186
VLSI array algorithms and architectures for RSA modular multiplication
187
VLSI array architecture for Reed-Solomon decoding
188
VLSI array architectures for pyramid vector quantization
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VLSI Array Design Under Constraint of Limited I/O Bandwidth
190
VLSI Array processing strctures of quadratic digital filters with LMS algorithm
191
VLSI array processor implementation of quasi-block state-space IIR digital filters
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VLSI Array processors
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VLSI array processors for linear-phase FIR filters
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VLSI array processors for linear-phase FIR filters
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VLSI array processors implementation of block-state IIR digital filters
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VLSI array processors: designs and applications
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VLSI array synthesis for polynomial GCD computation
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VLSI array synthesis for polynomial GCD computation and application to finite field division
199
VLSI array to speed up the computation of TV ghost canceler parameters
200
VLSI arrays for digital signal processing:Part I-A model identification approach to digital filter realizations
201
VLSI arrays for speech processing with linear predictive coding
202
VLSI ASIC design for MAC video processing integration in SGS-Thomson microelectronics chip set
203
VLSI asynchronous sequential circuit design
204
VLSI based analog power system emulator for fast contingency analysis
205
VLSI based design of a battery-operated digital hearing aid
206
VLSI based edge detection hardware accelerator for real time video segmentation system
207
VLSI based implementation of PCM MUX encoder for range telemetry system
208
VLSI Based Robust Router Architecture
209
VLSI based space vector pulse width modulation switching control
210
VLSI based tools for monitoring bus communication channels
211
VLSI beyond CMOS Devices: Nano, single electron and spintronic devices
212
VLSI Bio-Inspired Microsystem for Robust Microarrray Image Analysis and Recognition
213
VLSI bit-level systolic array for radar front-end signal processing
214
VLSI bit-sequential architectures for digital signal processing
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VLSI block placement using less flexibility first principles
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VLSI Block Placement With Alignment Constraints
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VLSI block placement with alignment constraints based on corner block list
218
VLSI block placement with directional graphs based on the new non-slicing representation
219
VLSI Building blocks for digital signal processing
220
VLSI CAD Education and Exercise Course with Public Domain Tools
221
VLSI CAD for emerging nanolithography
222
VLSI CAD Research at MCC
223
VLSI CAD Tool Integration Using the Ulysses Environment
224
VLSI cellular array of coupled delta-sigma modulators for random analog vector generation
225
VLSI challenges to more energy efficient devices
226
VLSI chaotic pulse coded modulator using neural type cells
227
VLSI characteristic of cellular automata and LFSR
228
VLSI Characterization of the Cryptographic Hash Function BLAKE
229
VLSI chip architecture for real-time ambiguity function computation
230
VLSI chip design
231
VLSI chip design of a CORDIC-based adaptive lattice filter
232
VLSI Chip Interconnection Technology Using Stacked Solder Bumps
233
VLSI chip set for 2D HDTV subband filtering with on-chip line memories
234
VLSI chip set for floating point vector processing
235
VLSI chip-architecture selection using reasoning based on fuzzy logic
236
VLSI chips supporting parallel bus interfacing and bus management
237
VLSI chipset for 16×16 ATM switch running at 500 Mbit/s per port
238
VLSI chip-set for personal computers
239
VLSI circuit architectures for Fermat number arithmetic in DSP applications
240
VLSI circuit challenges for integrated sensing systems
241
VLSI circuit complexity and decoding performance analysis for low-power RSC turbo-code and iterative block decoders design
242
VLSI circuit design concept for parallel iterative algorithms in nanoscale
243
VLSI circuit design using an object-oriented framework of evolutionary graph generation system
244
VLSI circuit design with built-in reliability using simulation techniques
245
VLSI circuit for programmable sorting
246
VLSI circuit partition using simulated annealing algorithm
247
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
248
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
249
VLSI circuit synthesis using a parallel genetic algorithm
250
VLSI Circuit Test Vector Compression Technique
251
VLSI Circuit Testing Using an Adaptive Optimization Model
252
VLSI circuits degradation due to ESD stress below ESD rating voltage
253
VLSI Circuits for a sampling digital acoustic energy meter
254
VLSI Circuits for Accurate Motion Estimation
255
VLSI circuits for adaptive digital beamforming in ultrasound imaging
256
VLSI circuits for decomposing binary integers into signed power-of-two terms
257
VLSI circuits for low-power high-speed asynchronous addition
258
VLSI circuits for multiplexed Star CNNs
259
VLSI circuits for optoelectronic neural network weight setting
260
VLSI Circuits Symposium Celebrates 20th Anniversary in June
261
VLSI circuits with fractal layout for spatial image decorrelation
262
VLSI CMOS fabrication modules combine with power device methods to produce 40 mΩ and 65 mΩ, 7 V logic level P-power FETs
263
VLSI CMOS implementation of the shuffleout ATM switch interconnection matrix
264
VLSI CMOS low-voltage log companding filters
265
VLSI compatible parallel fabrication of scalable few electron silicon quantum dots
266
VLSI Compatible Parallel Fabrication of Scalable Few Electron Silicon Quantum Dots
267
VLSI complexity of threshold gate COMPARISON
268
VLSI compressor design with applications to digital neural networks
269
VLSI computation of the partial DFT for (de)modulation in multi-channel OFDM system
270
VLSI Computational Architectures for the Arithmetic Cosine Transform
271
VLSI computing architectures for Haar transform
272
VLSI concentric partitioning using interior point quadratic programming
273
VLSI concepts for integrated voice/data terminals
274
VLSI concurrent error correcting adders and multipliers
275
VLSI configurable delay commutator for a pipeline split radix FFT architecture
276
VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration
277
VLSI considerations in the design of k-ary n-cube interconnection networks
278
VLSI core architecture for GF(p) elliptic curve crypto processor
279
VLSI costs of arithmetic parallelism: a residue reverse conversion perspective
280
VLSI cryogenic front-end for HPGe detectors based on a silicon-germanium technology
281
VLSI crypto-technology-application requirements
282
VLSI data demodulator for a microwave landing system
283
VLSI Data-Management
284
VLSI decoder architecture for embedded zerotree wavelet algorithm
285
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
286
VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX
287
VLSI decompositions for deBruijn graphs
288
VLSI delta-sigma cellular neural network for analog random vector generation
289
VLSI design [Book Review]
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VLSI design 101 - The test module
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VLSI Design 1992 The Fifth International Conference on VLSI Design
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VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
293
VLSI Design 2001. Fourteenth International Conference on VLSI Design
294
VLSI design 2003 Steering Committee
295
VLSI Design 2004 Conference Awards
296
VLSI design 2004 Conference Committee
297
VLSI design 2004 technical Program Committee
298
VLSI Design 2005 Conference Awards
299
VLSI Design 2006 Conference Awards
300
VLSI Design 2006 Conference Awards
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VLSI Design 2006 Conference Awards
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VLSI Design 2007 Awards
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VLSI Design 2008 Awards
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VLSI Design 2010 - Best Paper Awards
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VLSI Design 2011 Best Paper Awards
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VLSI Design 2011 Keynote Speakers
307
VLSI Design 2012 Best Paper Awards [4 awards]
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VLSI Design 2012 Conference Committee
309
VLSI Design 2013 Conference Committee
310
VLSI Design 2013 Conference Committee
311
VLSI Design 2015 Conference Committee
312
VLSI design af a DWT/modified efficient SPIHT based image codec
313
VLSI design and analysis of a critical-band processor for speech recognition
314
VLSI design and analysis of low power 6T SRAM cell using cadence tool
315
VLSI Design and Analysis of Multipliers for Low Power
316
VLSI Design and Application of a High-Voltage-Compatible SoC–ASIC in Bipolar CMOS/DMOS Technology for AC–DC Rectifiers
317
VLSI design and architecture of a VC-Merge capable crossbar switch on MPLS over ATM
318
VLSI design and CAD technology in Korea
319
VLSI design and CAE at Exeter University
320
VLSI design and comparative analysis of memory BIST controllers
321
VLSI Design and Education Center (VDEC) current status and future plan
322
VLSI design and fabrication for liquid crystal on silicon
323
VLSI design and implementation fuels the signal-processing revolution
324
VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform
325
VLSI design and implementation of a discrete cosine transform chip for video compression using high level synthesis tools
326
VLSI design and implementation of a fuzzy logic controller for engine idle speed
327
VLSI Design and Implementation of a High-Speed Multicast Switch Fabric
328
VLSI design and implementation of a self-testing systolic array chip for signal processing
329
VLSI design and implementation of a simple 4×4 Hopfield neural network
330
VLSI design and implementation of adaptive channel equalizer
331
VLSI design and implementation of an improved squaring circuit by combinational logic
332
VLSI design and implementation of analog CMOS 2nd generation current conveyors
333
VLSI design and implementation of CMOS current conveyors
334
VLSI design and implementation of high-speed RS(204,188) decoder
335
VLSI design and implementation of high-speed Viterbi decoder
336
VLSI Design and Implementation of Homophonic Security System
337
VLSI design and implementation of INTEL 8253IC using VHDL
338
VLSI design and implementation of low-complexity adaptive turbo-code encoder and decoder for wireless mobile communication applications
339
VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption
340
VLSI design and implementation of reconfigurable OFDM transceivers for software defined radio
341
VLSI design and implementation of the entropy decoder for multi-format video decoding algorithms
342
VLSI design and implementation of WCDMA channel decoder
343
VLSI design and realisation of a 4 input high speed fuzzy processor
344
VLSI Design and Simulation of A SIRM Fuzzy System - Diabetic Epilepsy Risk Level Classifier -A Case Study
345
VLSI design and system level verification for the Mini-Disc
346
VLSI design and test sequence in an academic environment: a case study
347
VLSI design and test: a unified approach
348
VLSI design and verification methodologies for automotive embedded systems
349
VLSI design and verification of the Imagine processor
350
VLSI design approach of complex motor control: case of direct torque control of AC machine
351
VLSI design at the undergraduate level
352
VLSI design automation activities at M.I.T.
353
VLSI design automation for the application system/400
354
VLSI design automation: An introduction
355
VLSI design challenges for gigascale integration
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VLSI Design Conference history
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VLSI Design Conference History
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VLSI Design Conference History
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VLSI Design Conference History
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VLSI Design Conference history
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VLSI Design Conference History
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VLSI Design Conference History
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VLSI Design Conference History
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VLSI Design Conference History
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VLSI Design Conference History
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VLSI Design Conference Steering Committee (2011)
367
VLSI Design Conference Steering Committee (2012)
368
VLSI Design Conference Steering Committee (2013)
369
VLSI Design Conference Steering Committee (2014)
370
VLSI Design Conference: history
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VLSI Design Considerations within Digital Radio
372
VLSI design courses enhanced by industrial participation: dual case study
373
VLSI design exchange with intellectual property protection in FPGA environment using both secret and public-key cryptography
374
VLSI design for a forward path neuron circuitry of a back propagation neural network
375
VLSI design for a new adaptive image compress coding
376
VLSI design for an adaptive equalizer using a residue number system architecture for magnetic channels
377
VLSI design for de-blocking filter of H.264 decoder
378
VLSI design for diminished-1 multiplication of integers modulo a Fermat number
379
VLSI Design for DVB-T2 LDPC Decoder
380
VLSI design for fault-dictionary based testability
381
VLSI design for high-speed LZ-based data compression
382
VLSI Design for High-Speed Sparse Parity-Check Matrix Decoders
383
VLSI Design for Low-Density Parity-Check Code Decoding
384
VLSI design for low-power data-adaptive motion estimation
385
VLSI design for MPEG-4 shape coding using a contour-based binary motion estimation algorithm
386
VLSI design for real-time signal processing based on biologically realistic neural models
387
VLSI design for SC-based speaker recognition
388
VLSI Design for SVM-Based Speaker Verification System
389
VLSI Design for Testability
390
VLSI design in heuristic environment
391
VLSI Design IP Protection: Solutions, New Challenges, and Opportunities
392
VLSI Design Language Standardization Effort in Japan
393
VLSI design methodologies for application specific binary sensors
394
VLSI design methodologies for digital signal processing
395
VLSI Design Methodology - the Problem of the 80´s for Microprocessor Design
396
VLSI Design Methodology Workshop
397
VLSI design methods using the concept of sea-of-wires
398
VLSI design network communication
399
VLSI design of 3D display processing chip for head-mounted display
400
VLSI design of a 1.0 GHz 0.6-μm 8-bit CLA using PLA-styled all-N-transistor logic
401
VLSI design of a bit-serial word-parallel sorter
402
VLSI design of a bus arbitration module for the 68000 series of microprocessors
403
VLSI design of a CORDIC-based derotator
404
VLSI design of a custom ASIC using VHDL for converting 12-bit binary to BCD
405
VLSI Design of a Depth Map Estimation Circuit Based on Structured Light Algorithm
406
VLSI design of a digital RFI cancellation scheme for VDSL transceivers
407
VLSI design of a high speed soft decision Viterbi detector
408
VLSI design of a high speed turbo decoder for 3rd generation satellite communication
409
VLSI Design of a High-Speed and Area-Efficient JPEG2000 Encoder
410
VLSI design of a high-speed CMOS image sensor with in-situ 2D programmable processing
411
VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture
412
VLSI design of a high-throughput discrete cosine transform for image compression systems
413
VLSI design of a high-throughput multi-rate decoder for structured LDPC codes
414
VLSI Design of a Large-Number Multiplier for Fully Homomorphic Encryption
415
VLSI design of a massively parallel processor
416
VLSI design of a modulo-extractor
417
VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter
418
VLSI design of a neural network based image processor
419
VLSI design of a neural processing element for the Boltzmann machine
420
VLSI design of a new infrared communication controller for wireless communications
421
VLSI design of a parallel architecture 2-D rank order filter
422
VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers
423
VLSI design of a priority arbitrator for shared buffer ATM switches
424
VLSI design of a processor for an integrated massively parallel architecture
425
VLSI design of a quaternary carry ripple adder
426
VLSI design of a quaternary multiplier with direct generation of partial products
427
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
428
VLSI design of a robotic controller for a dual axis manipulator element
429
VLSI design of a routing switch for the SpaceWire serial link standard
430
VLSI design of a sigma-delta bitstream FIR filter
431
VLSI design of a systolic array for finding maximal overlaps of strings
432
VLSI Design of a Wavelet Processing Core
433
VLSI design of active filters
434
VLSI design of an 8-bit fixed point CORDIC processor with extended operation set
435
VLSI design of an algebraic-integer signal processor
436
VLSI design of an ATM switch with automatic fault detection
437
VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking
438
VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking
439
VLSI design of an interference canceller for QPSK OFDM-IDMA systems
440
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm
441
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing
442
VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes
443
VLSI design of bit-retimed and pipelined recursive filters
444
VLSI design of cellular neural networks with annealing and optical input capabilities
445
VLSI design of clustering analyser using systolic arrays
446
VLSI design of CMOS image-reject LNA for 950-MHz wireless receivers
447
VLSI design of compact and high-precision analog neural network processors
448
VLSI design of densely-connected array processors
449
VLSI Design of DFE Equalizer for ATSC DTxR System
450
VLSI Design of Diminished-One Modulo 2^{n}+1 Adder Using Circular Carry Selection
451
VLSI design of DLMS adaptive IIR filters for high speed echo cancellation
452
VLSI design of domain specific architecture
453
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
454
VLSI design of dynamically reconfigurable array processor-DRAP
455
VLSI design of ECG QRS complex detection using Multiscale Mathematical Morphology
456
VLSI design of echo cancelers for the HDSL system
457
VLSI Design of Edge-Preserving Coding Artifacts Reduction for Display Processing
458
VLSI design of Ethernet CSMA/CD physical layer in HUB based on FSM/VHDL and its simulation
459
VLSI design of Extreme Value Detection based fast algorithm for H.264/AVC intra prediction
460
VLSI design of fast DCTQ-IQIDCT processor for real time image compression
461
VLSI design of fast fractal image encoder
462
VLSI design of fuzzy logic controller
463
VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder
464
VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel
465
VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
466
VLSI design of high-throughput processing element for real-time particle filtering
467
VLSI design of HW/SW interface logic in FC-2
468
VLSI design of inner-product computers using distributed arithmetic
469
VLSI design of inverse-free Berlekamp-Massey algorithm
470
VLSI Design of ISM Band RF Down Conversion Mixer
471
VLSI design of large-scale soft-output MIMO detection using conjugate gradients
472
VLSI design of low power SRAM architectures for FPGAs
473
VLSI design of mixed radix FFT Processor for MIMO OFDM in wireless communications
474
VLSI design of modulo adders/subtractors
475
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
476
VLSI design of multi-rate arrays for DSP algorithm
477
VLSI design of OFDM baseband transceiver with dynamic spectrum access
478
VLSI design of on-line add/multiply algorithms
479
VLSI design of optically coupled neural networks
480
VLSI design of optimization and image processing cellular neural networks
481
VLSI design of parallel sorter based on modified PCM algorithm and Batcher´s odd-even mergesort
482
VLSI design of power efficient Carry Skip Adder using TSG & Fredkin reversible gate
483
VLSI design of radial functions hardware generator for neural computations
484
VLSI design of rate 2/3 Viterbi decoders
485
VLSI design of Reed-Solomon decoder architectures
486
VLSI design of Reed-Solomon decoder based on new architecture of modified Euclidean algorithm
487
VLSI design of resource shared complex-QMF bank for HE-AAC decoder
488
VLSI design of sequential minimal optimization algorithm for SVM learning
489
VLSI design of spread spectrum encoding low power RFID tag baseband processor
490
VLSI design of stability routing protocol for sensors in MANETs
491
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
492
VLSI design of the reassembly management for ATM/AAL
493
VLSI design of the shuffle-exchange network for 2D fast transforms
494
VLSI design of the shuffle-exchange network for 2D fast transforms
495
Vlsi Design Of The Tiny Risc Microprocessor
496
VLSI design of turbo decoder for integrated communication system-on-chip applications
497
VLSI design of universal color conversion circuit
498
VLSI design optimization of input/output-buffered broadband ATM switches
499
VLSI design parsing
500
VLSI design synthesis with testability
501
VLSI design teaching in a computer science department
502
VLSI design techniques and strategies for implementing adaptive equalizer
503
VLSI design techniques in teaching and research
504
VLSI design theory: tenacious myths and economic constraints
505
VLSI design to unify IDCT and IQ circuit for multistandard video decoder
506
VLSI design training and education in the University of Cantabria within EUROCHIP
507
VLSI design training with the help of the World Wide Web
508
VLSI design within an integrated engineering course
509
VLSI design, computer science and engineering issues
510
VLSI design: developments in teaching and research at the University of Essex
511
VLSI Designer´s interface
512
VLSI Designer´s Interface
513
VLSI Designer´s interface
514
VLSI Designer´s interface
515
VLSI Designer´s interface
516
VLSI Designer´s interface
517
VLSI designer´s interface
518
VLSI Designer´s interface
519
VLSI Designer´s interface
520
VLSI Designer´s interface
521
VLSI designer´s interface
522
VLSI designer´s interface
523
VLSI Designer´s interface
524
VLSI Designer´s Interface
525
VLSI Designer´s Interface
526
VLSI Designer´s interface
527
VLSI designs for high-speed Huffman decoder
528
VLSI designs for redundant binary-coded decimal addition
529
VLSI development of a global memory interface controller
530
VLSI development of a reconfigurable multi-user Viterbi decoder
531
VLSI development of smart-pixel ICs: a hybrid DSP core and a multi-threaded programmable DSP
532
VLSI Device fabrication using a unique, highly-selective Si3N4dry etching
533
VLSI device parameters extraction for radiation hardness modeling with SPICE
534
VLSI digital demodulator co-processor
535
VLSI digital polarity correlator based on an overloading counter technique
536
VLSI digital signal processing education
537
VLSI Digital signal processor (PSI)
538
VLSI Dynamic nMOS design constraints due to drain induced primary and secondary impact ionization
539
VLSI dynamically reconfigurable hardware for finite state machine design and analyses
540
VLSI Echo Cancelers For Underwater Acoustic Communications
541
VLSI echo cancellation filter
542
VLSI Education for Computer Science and Engineering Students through Virtual Labs
543
VLSI education in Britain
544
VLSI education in Institut Teknologi Bandung Indonesia
545
VLSI Education: Past, Present and Future
546
VLSI efficient discrete-time cellular neural network processor
547
VLSI Electronics Design and Testing for the Silicon Drift Sensor System of the ALICE Experiment
548
VLSI Electronics: Microstructure Science. Volume 12: Silicon Materials
549
VLSI fast initial placement with abutment constraints and L-shaped/T-shaped blocks based on less flexibility first principles
550
VLSI floating-point processors
551
VLSI Floorplan Based on Less Flexibility First Principle and Linear Programming
552
VLSI floorplan generation and area optimization using AND-OR graph search
553
VLSI floorplanning based on Particle Swarm Optimization
554
VLSI floorplanning design using clonal selection algorithm
555
VLSI floorplanning with boundary constraints based on corner block list
556
VLSI focal-plane array processor for morphological image processing
557
VLSI for 5000-word continuous speech recognition
558
VLSI for analog/digital communications
559
VLSI for ATM network management
560
VLSI for digital television
561
VLSI for high-performance graphic control utilizing multiprocessor architecture
562
VLSI for multimedia U-NII WLANs
563
VLSI for OFDM
564
VLSI friendly computation reduction scheme in H.264/AVC motion estimation
565
VLSI Friendly ECG QRS Complex Detector for Body Sensor Networks
566
VLSI friendly edge gradient detection based multiple reference frames motion estimation optimization for H.264/AVC
567
VLSI friendly fast CU/PU mode decision for HEVC intra encoding: Leveraging convolution neural network
568
VLSI friendly me search window buffer structure optimization and algorithm verification for high definition H.264/AVS video encoder
569
VLSI fuzzy chip and inference accelerator board systems
570
VLSI Gate array prime radix Fourier transform processor
571
VLSI Hamming neural net showing digital decoding
572
VLSI hardware architecture for complex fuzzy systems
573
VLSI hardware design by computer science students: how early can they start? How far can they go?
574
VLSI hardware design of QR-factorizer for a V-BLAST detector
575
VLSI hardware evaluation of the stream ciphers Salsa20 and ChaCha, and the compression function Rumba
576
VLSI hardware for example-based learning
577
VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters
578
VLSI hybrid DC-DC regulator
579
VLSI IC emission models for system simulation
580
VLSI IC of IEC/ISA data link layer FieldBus
581
VLSI Image Processing
582
VLSI image processor using analog programmable synapses and neurons
583
VLSI Impact on Electronics in the 80´s and its Applications
584
VLSI Impact on microprocessor evolution, usage, and system design
585
VLSI Impact on Microprocessor Evolution, Usage, and System Design
586
VLSI implementable neural network for solving linear programming problems efficiently
587
VLSI implementation and complexity comparison of residue generators modulo 3
588
VLSI implementation and optimization design of Reed-Solomon decoder in QAM demodulation chip
589
VLSI implementation and performance evaluation of adaptive filters for impulse noise removal
590
VLSI implementation and performance of turbo decoding stopping criteria
591
VLSI implementation considerations for turbo decoding using a low latency log-MAP
592
VLSI implementation for a low power mobile OFDM receiver ASIC
593
VLSI implementation for Epileptic Seizure Prediction System based on wavelet and chaos theory
594
VLSI implementation for HVRI algorithm in pattern recognition
595
VLSI implementation for low density parity check decoder
596
VLSI implementation for low-complexity full-search motion estimation
597
VLSI implementation for MAC-level DWT architecture
598
VLSI implementation for one-dimensional multilevel lifting-based wavelet transform
599
VLSI Implementation for Portable Application Oriented MPEG-4 Audio Codec
600
VLSI implementation for real-time extraction of direction vectors from binary images for pattern recognition applications
601
VLSI implementation in multiple-valued logic of an FIR digital filter using residue number system arithmetic
602
VLSI implementation issues of lattice decoders for MIMO systems
603
VLSI implementation issues of TURBO decoder design for wireless applications
604
VLSI Implementation of 1/2 Viterbi Decoder for IEEE P802.15-3a UWB Communication
605
VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme
606
VLSI implementation of 2-D discrete wavelet transform for real-time video signal processing
607
VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme
608
VLSI implementation of 350 MHz 0.35 μm 8 bit merged squarer
609
VLSI implementation of 3-D sound generator
610
VLSI Implementation Of 3-D Sound Generator
611
VLSI implementation of 3D sound movement
612
VLSI implementation of a 100 MHz pipelined ADPCM codec chip
613
VLSI implementation of a 100-μW multirate FSK receiver
614
VLSI implementation of a 16×16 DCT
615
VLSI implementation of a 16×16 discrete cosine transform
616
VLSI implementation of a 200-MHz 16×16 left-to-right carry-free multiplier in 0.35 μm CMOS technology for next-generation DSPs
617
VLSI implementation of a 256×256 crossbar interconnection network
618
VLSI implementation of a 2-D DCT in a compiler
619
VLSI implementation of a 300-MHz 0.35-μm CMOS 32-bit auto-reloadable binary synchronous counter with optimal test overhead delay
620
VLSI implementation of a 32-bit Kozen formulation Ladner/Fischer parallel prefix adder
621
VLSI Implementation of a 4×4 MIMO-OFDM transceiver with an 80-MHz channel bandwidth
622
VLSI implementation of a 5-trit full adder
623
VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System
624
VLSI implementation of a binary neural network-two case studies
625
VLSI Implementation of a Bio-Inspired Olfactory Spiking Neural Network
626
VLSI implementation of a bi-processor architecture for generic subband coding
627
VLSI implementation of a CDMA blind adaptive interference-mitigating detector
628
VLSI implementation of a Cellular Neural Network with programmable control operator
629
VLSI implementation of a CMOS power supply from electromagnetic waves
630
VLSI implementation of a cochlear model
631
VLSI implementation of a color map inversion algorithm [color printer applications]
632
VLSI implementation of a complete chip set for an MPEG2 real-time encoder
633
VLSI implementation of a conductance-based multi-synapse using switched-capacitor circuits
634
VLSI implementation of a copy network for a multicast ATM switch
635
VLSI implementation of a CORDIC SVD processor
636
VLSI Implementation of a Cryptography-Oriented Reconfigurable Array
637
VLSI Implementation of a Decimation Filter for Sigma-Delta AD Converters
638
VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair
639
VLSI implementation of a double-layer single cell RD-CNN for motion control
640
VLSI Implementation of a DPCM Compression Algorithm for Digital TV
641
VLSI implementation of a DWT architecture
642
VLSI implementation of a dynamic retina
643
VLSI implementation of a fairness ATM buffer system
644
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding
645
VLSI implementation of a fast radix-4 SRT division
646
VLSI Implementation of a fast rank order filtering algorithm
647
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
648
VLSI implementation of a feature mapping neural network
649
VLSI implementation of a floating-point divider
650
VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept
651
VLSI implementation of a foveal polygon segmentation algorithm
652
VLSI Implementation of a Fractal Image Coding Algorithm
653
VLSI implementation of a fully parallel stochastic neural network
654
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits
655
VLSI implementation of a functional neural network
656
VLSI implementation of a generic discrete transform processor for real-time applications
657
VLSI implementation of a hardware-optimized lattice reduction algorithm for WiMAX/LTE MIMO detection
658
VLSI implementation of a high performance and low power 32-bit multiply-accumulate unit
659
VLSI implementation of a high speed block-cipher module
660
VLSI implementation of a high speed second order sigma-delta modulator with high-performance integrators
661
VLSI implementation of a high speed single precision floating point unit using verilog
662
VLSI implementation of a high-performance 32-bit RISC microprocessor
663
VLSI implementation of a high-speed and low-power punctured Viterbi decoder
664
VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition
665
Vlsi Implementation Of A High-throughput Cordic Processor For Both Angle Calculation And Vector Rotation
666
VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder
667
VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes
668
VLSI Implementation of a Key Distribution Server Based Data Security Scheme for RFID System
669
VLSI Implementation of a Lattice Reduction Algorithm for Low-Complexity Equalization
670
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding
671
VLSI implementation of a learning actractor neuronal network (LANN)
672
VLSI Implementation of a linear systolic array
673
VLSI implementation of a lossless ECG encoder design with fuzzy decision and two-stage Huffman coding for wireless body sensor network
674
VLSI implementation of a low bit-rate video codec
675
VLSI implementation of a low complexity 4×4 MIMO sphere decoder with table enumeration
676
VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection
677
VLSI Implementation of a Low-Cost High-Quality Image Scaling Processor
678
VLSI implementation of a low-energy soft digital filter
679
VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity
680
VLSI implementation of a low-power antilogarithmic converter
681
VLSI implementation of a maximum-likelihood decoder for the Golay (24, 12) code
682
VLSI implementation of a mixed bio-signal lossless data compressor for portable brain-heart monitoring systems
683
VLSI implementation of a modular and programmable neural architecture
684
VLSI implementation of a modular ANN chip for character recognition
685
VLSI implementation of a module for realization of basic t-norms on fuzzy hardware
686
VLSI implementation of a multi-amplitude continuous phase receiver
687
VLSI implementation of a multicast ATM switch
688
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
689
VLSI implementation of A multi-standard MIMO symbol detector for 3GPP LTE and WiMAX
690
VLSI implementation of a neural network classifier
691
VLSI implementation of a neural network classifier based on the saturating linear activation function
692
VLSI implementation of a neural network for solving linear second order parabolic PDE
693
VLSI implementation of a neural network model
694
VLSI implementation of a new bit-level pipelined architecture for 2-D allpass digital filters
695
VLSI implementation of a new block cipher
696
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation
697
VLSI IMPLEMENTATION OF A NONLINEAR IMAGE INTERPOLATION FILTER
698
VLSI implementation of a nonlinear image interpolation filter
699
VLSI Implementation of a Nonlinear Neuronal Model: A "Neural Prosthesis" to Restore Hippocampal Trisynaptic Dynamics
700
VLSI implementation of a novel algorithm for binary-negabinary code conversion
701
VLSI implementation of a pel-by-pel motion estimator
702
VLSI implementation of a pulse Hebbian learning law
703
VLSI implementation of a quasi-ml, energy efficient fixed complexity sphere decoder for MIMO communication system
704
VLSI implementation of a real-time operating system
705
VLSI implementation of a real-time video watermark embedder and detector
706
VLSI implementation of a real-time vision based lane departure warning system
707
VLSI implementation of a realtime wavelet video coder
708
VLSI implementation of a reconfigurable cellular neural network containing local logic (CNNL)
709
VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter
710
VLSI implementation of a reduced memory bandwidth real-time EZW video coder
711
VLSI implementation of a reversible variable length encoder/decoder
712
VLSI implementation of a scalable K-best MIMO detector
713
VLSI implementation of a second-order digital filter
714
VLSI Implementation of a Selective Median Filter
715
VLSI implementation of a selective median filter
716
VLSI implementation of a self-checking self-exercising memory system
717
VLSI implementation of a sequential Monte Carlo receiver
718
VLSI implementation of a shift-enabled reconfigurable array
719
VLSI implementation of a sigma-delta bitstream FIR filter
720
VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers
721
VLSI Implementation of a Skin Detector Based on a Neural Network
722
VLSI implementation of a soft bit-flipping decoder for PG-LDPC codes
723
VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems
724
VLSI implementation of a switch fabric for mixed ATM and IP traffic
725
VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection
726
VLSI implementation of a transconductance mode continuous BAM with on chip learning and dynamic analog memory
727
VLSI implementation of a tree searched vector quantizer
728
VLSI implementation of a variable-length pipeline scheme for data-driven processors
729
VLSI implementation of a vector quantization processor
730
VLSI implementation of a wavelet image compression technique using replicated coding/decoding cells
731
VLSI implementation of a wide band, high dynamic range digital drop receiver
732
VLSI implementation of a wide-band sonar receiver
733
VLSI implementation of a WiMAX/LTE compliant low-complexity high-throughput soft-output K-Best MIMO detector
734
VLSI implementation of a wormhole router using virtual channels
735
VLSI implementation of adaptive bit/serial IIR filters
736
VLSI implementation of adaptive current controller for high bright LED lighting
737
VLSI implementation of adaptors using systolic arrays
738
VLSI implementation of adders for high speed ALU
739
VLSI implementation of advance encryption algorithm using index technique
740
VLSI Implementation of Advanced Encryption Standard
741
VLSI implementation of an 855 Mbps high performance soft-output K-Best MIMO detector
742
VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications
743
VLSI Implementation of an Adaptive Edge-Enhanced Image Scalar for Real-Time Multimedia Applications
744
VLSI implementation of an adaptive equalizer for ATSC digital TV receivers
745
VLSI implementation of an AES algorithm resistant to Differential Power Analysis attack
746
VLSI implementation of an application-specific vision chip for overtake monitoring, real time eye tracking, and automated visual inspection
747
VLSI implementation of an area-efficient architecture for the Viterbi algorithm
748
VLSI implementation of an associative content addressable memory based on Hopfield network model
749
VLSI implementation of an associative memory using temporal relations
750
VLSI implementation of an associative memory using temporal relations
751
VLSI implementation of an edge detector based on Sobel operator
752
VLSI Implementation of an Edge-Oriented Image Scaling Processor
753
VLSI implementation of an effective lattice reduction algorithm with fixed-point considerations
754
VLSI implementation of an efficient Fused Add-Multiply unit using Constant-time addition
755
VLSI Implementation of an Efficient Pre-Trace Back Approach for Viterbi Algorithm
756
VLSI implementation of an eight-state clustering based sequence equalizer
757
VLSI implementation of an entropy coder and decoder for advanced TV applications
758
Vlsi implementation of an entropy encoder for H.264/AVC baseline
759
VLSI implementation of an extended Hamming neural network for non-binary pattern recognition
760
VLSI implementation of an image compression algorithm with a new bit rate control capability
761
VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical Applications
762
VLSI implementation of an improved multiplier for FFT computation in biomedical applications
763
VLSI implementation of an OFB processor for encryption of real-time data
764
VLSI Implementation of Area-efficient List Sphere Decoder
765
VLSI Implementation of Area-efficient List Sphere Decoder
766
VLSI implementation of ART1 memories
767
VLSI implementation of artificial neural network based digital multiplier and adder
768
VLSI Implementation of Autocorrelator and CORDIC Algorithm for OFDM Based WLAN
769
VLSI Implementation of Balanced Binary Tree Decomposition Based 2048-Point FFT/IFFT Processor for Mobile WI-Max
770
VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory
771
VLSI implementation of belief-propagation-based stereo matching with linear-model message update
772
VLSI implementation of BER measurement for wireless communication system
773
VLSI implementation of binary relation inference network in solving shortest path problems
774
VLSI implementation of bit serial architecture based multiplier in floating point arithmetic
775
VLSI implementation of bit-parallel word-serial multiplier in GF(2233)
776
VLSI implementation of camera digital signal processor for document projection system
777
VLSI Implementation of CAVLC Decoder for H.264/AVC Video Decoding
778
VLSI implementation of CAVLC decoder with power Optimized for H.264/AVC video decoding
779
VLSI implementation of cellular neural network universal machine
780
VLSI implementation of cellular neural network universal machine
781
VLSI implementation of cellular neural networks
782
VLSI implementation of color interpolation in color difference spaces
783
VLSI implementation of conjugate gradient based mobile user tracking system
784
VLSI implementation of controllers for communication protocols from their Petri net models
785
VLSI implementation of CORDIC angle units
786
VLSI implementation of coupled MRF model using pulse-coupled phase oscillators
787
VLSI implementation of CRC-32 for 10 Gigabit Ethernet
788
VLSI implementation of cross-coupled MOS resistor circuits
789
VLSI implementation of current mode analog multiplier
790
VLSI implementation of decoder for decompressing fractal-based compressed image
791
VLSI implementation of digital channeliser using distributed arithmetic
792
VLSI implementation of digital compensators and predictive PID controllers
793
VLSI Implementation of digital frequency sensors as hardware countermeasure
794
VLSI implementation of digital receivers for paging and PCS
795
VLSI implementation of digit-recurrent CORDIC with constant scaling factor
796
VLSI implementation of discrete cosine transform and Intra prediction
797
VLSI implementation of discrete Mellin transform for real time scale analysis of images
798
VLSI implementation of discrete wavelet transform
799
VLSI implementation of discrete wavelet transform
800
VLSI implementation of discrete wavelet transform
801
VLSI implementation of DNA cryptography using quantum key exchange
802
VLSI implementation of DS-CDMA receiver using asynchronous design techniques
803
VLSI implementation of DVB/RCS turbo code
804
VLSI implementation of dynamically reconfigurable hardware-based cryptosystem
805
VLSI implementation of early branch prediction circuits for high performance computing
806
VLSI implementation of edge detector and vector quantizer for very low bitrate video encoding
807
VLSI implementation of efficient image watermarking algorithm
808
VLSI implementation of efficient split radix FFT based on distributed arithmetic
809
VLSI implementation of electronics module of a thermal imaging system
810
VLSI implementation of embedded back-end for photo-acoustic based continuous noninvasive blood glucose monitoring system
811
VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal Technique
812
VLSI implementation of fast addition using quaternary Signed Digit number system
813
VLSI Implementation of Fast Connected Component Labeling Using Finite State Machine Based Cell Network
814
VLSI implementation of fast convolution
815
VLSI implementation of fast Fourier transformation for OFDM-based high-speed wireless applications
816
VLSI implementation of fractal image compression processor for moving pictures
817
VLSI implementation of fractional motion estimation interpolation for high efficiency video coding
818
VLSI implementation of full pixel motion estimation processor for MPEG-4 AS profile
819
VLSI Implementation of fully pipelined multiplierless 2D DCT/IDCT architecture for JPEG
820
VLSI implementation of fuzzy adaptive resonance and learning vector quantization
821
VLSI implementation of genetic four-step search for block matching algorithm
822
VLSI implementation of gigabit ethernet with data compression and decompression
823
VLSI implementation of Gm-C filter using modified Nauta OTA with double CMOS pair
824
VLSI implementation of GRBF (Gaussian radial basis function) networks
825
VLSI implementation of GSC architecture with a new ripple carry adder
826
VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL
827
VLSI implementation of high performance burst mode for 128-bit block ciphers
828
VLSI Implementation of High Performance RSA Algorithm Using Vedic Mathematics
829
VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application
830
VLSI implementation of high speed digital filters using direct form delta structures
831
VLSI implementation of high speed two-dimensional state-space recursive filtering
832
VLSI implementation of high speed wave digital filters based on a restricted coefficient set
833
VLSI implementation of high speed wave digital filters based on a restricted coefficient set
834
VLSI implementation of high throughput DSP using finite ring arithmetic
835
VLSI Implementation of High-Performance Error Concealment Processor for TV Broadcasting
836
VLSI Implementation of High-Speed Cellular Automata Encryption Algorithm
837
VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter application
838
VLSI implementation of high-speed SHA-256
839
VLSI implementation of high-throughput parallel H.264/AVC baseline intra-predictor
840
VLSI Implementation of High-Throughput SISO-OFDM and MIMO-OFDM Transceivers
841
VLSI implementation of high-throughput, low-energy, configurable MIMO detector
842
VLSI implementation of hybrid QR code generation system
843
VLSI implementation of image scaling processor
844
VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding
845
VLSI implementation of Inverse Discrete Wavelet Transform for JPEG 2000
846
VLSI implementation of invisible digital watermarking algorithms towards the development of a secure JPEG encoder
847
VLSI implementation of locally connected neural network for solving partial differential equations
848
VLSI implementation of low -complexity Reed Solomon decoder
849
VLSI Implementation of Low Power High Throughput Low Density Parity Check Code Decoder for Optical Communication
850
VLSI Implementation of Low Power Multiple Single Input Change (MSIC) Test Pattern Generation for BIST Scheme
851
VLSI implementation of low-power cost-efficient lossless ECG encoder design for wireless healthcare monitoring application
852
VLSI implementation of low-power high-quality color interpolation processor for CCD camera
853
VLSI implementation of Mallat´s fast discrete wavelet transform algorithm with reduced complexity
854
VLSI implementation of memory design applied to median filter
855
VLSI implementation of MIMO detection using the sphere decoding algorithm
856
VLSI implementation of minimum order state-space structures for adaptive digital filters
857
VLSI implementation of modified daubechies architecture for brain disease detection and identification
858
VLSI implementation of mod-p multipliers using homomorphisms and hybrid cellular automata
859
VLSI implementation of modulo multiplication using carry free addition
860
VLSI implementation of modulo-arithmetic units using 2-D cellular automata
861
VLSI implementation of moment invariants for automated inspection
862
VLSI implementation of MQ decoder in JPEG2000
863
VLSI implementation of multiple binomial windows for real-time image processing
864
VLSI implementation of multiplier-free low power baseband filter for CDMA systems
865
VLSI implementation of multiprocessor system
866
VLSI implementation of neural networks
867
VLSI implementation of neural networks with application to signal processing
868
VLSI implementation of neural-type cell with MOS linear resistor
869
VLSI implementation of neuromime pulse generator for Eckhorn neurons
870
VLSI implementation of new arithmetic residue to binary decoders
871
Vlsi implementation of nonlinear variable cutoff high pass filter algorithm
872
VLSI implementation of novel fast confluence ICA algorithm for signal processing applications
873
VLSI implementation of Ogg Vorbis decoder for embedded applications
874
VLSI implementation of on board processing subsystems for satellite channels
875
VLSI implementation of online digital watermarking technique with difference encoding for 8-bit gray scale images
876
VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor
877
VLSI implementation of password (PIN) authentication unit
878
VLSI implementation of Phong shader in 3D graphics
879
VLSI implementation of Piecewise Approximated antilogarithmic converter
880
VLSI implementation of pipelined linear system solver
881
VLSI implementation of pipelined sphere decoding with early termination
882
VLSI implementation of portable MPEG-4 audio decoder
883
VLSI implementation of priority selection algorithm to select tags using RFID system
884
VLSI implementation of pulse activated synapses
885
VLSI implementation of pulse coded winner take all networks
886
VLSI implementation of pulse density modulated neural network structure
887
VLSI implementation of rake receiver for IS-95 CDMA testbed using FPGA
888
VLSI implementation of real-time image rotation
889
VLSI implementation of real-time image segmentation
890
VLSI Implementation of real-time Kalman filter
891
VLSI implementation of real-time motion compensated beamforming in synthetic transmit aperture imaging
892
Vlsi Implementation Of Real-time Parallel Dct/dst Lattice Structures For Video Communications
893
VLSI implementation of receptive fields for smart vision sensors
894
VLSI implementation of reconfigurable cells for RFU in embedded processors
895
VLSI implementation of reconfigurable processing modulefor binary and grayscale image processing
896
VLSI implementation of reconfigurable SRRC filters with automatic code generation
897
VLSI implementation of reduced complexity wallace multiplier using energy efficient CMOS full adder
898
VLSI implementation of reduced resource allocation for modified carry look-ahead adder
899
VLSI implementation of rehabituation
900
VLSI implementation of residue adders based on binary adders
901
VLSI implementation of residue-to-binary converters for digital signal processing
902
VLSI implementation of rotations in pseudo-Euclidean spaces
903
VLSI implementation of routing tables: tries and CAMs
904
VLSI implementation of single bit control system processor with efficient code density
905
VLSI implementation of single chip encoder/decoder for low bitrate visual communication
906
VLSI implementation of single chip JPEG codec
907
VLSI implementation of SISO arithmetic decoders for joint source channel coding
908
VLSI implementation of sliding window DFT
909
VLSI implementation of smart imaging system using two-dimensional cellular automata
910
VLSI implementation of soft output Viterbi equalizers for mobile radio applications
911
VLSI implementation of sorting network for ACSFD in WSN
912
VLSI implementation of spatial prediction based image compression scheme
913
VLSI implementation of STM-1 Framer and De-Framer
914
VLSI Implementation of Sub-pixel Interpolator for H.264/AVC Encoder
915
VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells
916
VLSI implementation of synchronization algorithms in a 100 Mbit/s digital receiver
917
VLSI implementation of synchronizer and pipelined CORDIC in OFDM receiver for fourth generation wireless LAN applications
918
VLSI implementation of Tausworthe random number generator for parallel processing environment
919
VLSI implementation of ternary gates using Tanner Tool
920
VLSI implementation of the advanced encryption standard system with error detection
921
VLSI implementation of the arithmetic Fourier transform
922
VLSI implementation of the CORDIC algorithm using redundant arithmetic
923
VLSI implementation of the hippocampus on nonlinear system model
924
VLSI implementation of the keyed-hash message authentication code for the wireless application protocol
925
VLSI Implementation of the List Sphere Algorithm
926
VLSI implementation of the metering signal generator for switching system analog terminations
927
VLSI implementation of the motion estimator with two-dimensional data-reuse
928
Vlsi Implementation Of The Motion Estimator With Two-dimensional Data-reuse
929
VLSI implementation of the quadratic-spline W-transform for multi-resolution image processing
930
VLSI Implementation Of The Realtime Image Processing Parallel Architecture Gflops
931
VLSI implementation of the sphere decoding algorithm
932
VLSI implementation of the SS7 TCAP
933
VLSI implementation of the universal 2-D CAT/ICAT system
934
VLSI implementation of the universal one-dimensional CAT/ICAT
935
VLSI implementation of the variable length pipeline scheme for data-driven processors
936
VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode
937
VLSI Implementation Of Two-dimensional DCT Processor In Real Time For Video Codec
938
VLSI implementation of two-dimensional DCT processor in real time for video codec
939
VLSI implementation of two-dimensional digital filters via two-dimensional filter chips
940
VLSI implementation of two-dimensional digital filters via two-dimensional filter chips
941
VLSI Implementation of two-dimensional generalized mean filter
942
VLSI implementation of type-2 fuzzy inference processor
943
VLSI implementation of universal random number generator
944
VLSI implementation of uterus image segmentation using multi-feature EM algorithm based on Gabor filter: FPGA implementation of uterus image segmentation using multi-feature EM algorithm based on Gabor filter
945
VLSI implementation of variable resolution image compression
946
VLSI implementation of vector quantization using distributed arithmetic
947
VLSI implementation of very low-power motion estimator for scalable coding systems
948
VLSI implementation of very-high-order FIR filters
949
VLSI implementation of visible watermarking for secure digital still camera design
950
Vlsi Implementation Of Visual Block Pattern Truncation Coding
951
VLSI implementation of visual block pattern truncation coding
952
VLSI implementation of wave digital filters using systolic arrays
953
VLSI Implementation of Wavelet Based Robust Image Watermarking Chip
954
VLSI implementation of wireless bi-directional communication circuits for micro-stimulator
955
VLSI implementation of wireless power and data transmission circuits for micro-stimulator
956
VLSI implementation with double cipher and media processing for ad-hoc network
957
VLSI implementation-oriented (3, k)-regular low-density parity-check codes
958
VLSI implementations For A Subband Based HDVT Codec
959
VLSI implementations of ATM buffer management
960
VLSI Implementations of Cernsus Computations: Meshes vs. Trees vs. Compromises
961
VLSI implementations of CNNs for image processing and vision tasks: single and multiple chip approaches
962
VLSI implementations of communication protocols-a survey
963
VLSI implementations of efficient isotropic flexible 2D convolvers
964
VLSI implementations of electronic neural networks: an example in character recognition
965
VLSI implementations of fuzzy logic controllers for rate-adaptive pacemakers
966
VLSI implementations of image and video multimedia processing systems
967
VLSI Implementations of Low-Power Leading-One Detector Circuits
968
VLSI implementations of neural-like networks for finite ring computations
969
VLSI implementations of stereo matching using Dynamic Programming
970
VLSI implementations of switched-capacitor filter
971
VLSI implementations of the cryptographic hash functions MD6 and ïrRUPT
972
VLSI implementations of the triple-DES block cipher
973
VLSI implementations of threshold logic-a comprehensive survey
974
VLSI implemented data-aided ML parameter estimators of PSK burst modems
975
VLSI implemented ML joint carrier phase and timing offsets estimator for QPSK/OQPSK burst modems
976
VLSI improvements in a binary multiplier based on analog digits
977
VLSI in Communications
978
VLSI In Communications [Guest Editorial]
979
VLSI in consumer electronics
980
VLSI in consumer electronics
981
VLSI in Japan: The Big Leap Forward 1980-1981
982
VLSI in mobile communications
983
VLSI in the Laboratory the Office the Factory the Home
984
VLSI industry-university interaction
985
VLSI integration of SiGe epitaxial base bipolar transistors
986
VLSI interconnect delay analysis method for ramp input signal
987
VLSI interconnect design automation using quantitative and symbolic techniques
988
VLSI interconnect linewidth variation: a method to characterize depth of focus and proximity effects
989
VLSI interconnect modeling at multi-GHz frequencies incorporating inductance
990
VLSI interconnect process integration
991
VLSI interconnect signal analysis using a projection framework method
992
VLSI interconnects at multi GHz frequencies incorporating inductance
993
VLSI IP companies: changing environment and business model
994
VLSI issues in memory-system design for video signal processors
995
VLSI layout compaction using radix priority search trees
996
VLSI layout compaction with conditional constraints
997
VLSI Layout Compaction with Grid and Mixed Constraints
998
VLSI layout generation of a programmable CRC chip
999
VLSI layout of a pipelined multiplier
1000
VLSI legalization with minimum perturbation by iterative augmentation
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