ليست عنوان مقالات لاتين فني مهندسي GaSe electro-optic sensors for ultrabroadband detection of multi-THz field transients Gate-substrated Structure to Improve FED Performance

Gate Influence on the Layout Sensitivity of $\\hbox {Si}_{1 - x}\\hbox {Ge}_{x} \\hbox {S/D}$ and $\\hbox</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>436</div><a href='49/974614.htm'>Gate Injection Transistor (GIT)—A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>437</div><a href='49/3447939.htm'>Gate input reconfiguration for combating soft errors in combinational circuits</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>438</div><a href='49/1951257.htm'>Gate insulating layer impact on the extension profile of the sub-50 nm p-MOSFET</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>439</div><a href='49/1895475.htm'>Gate insulation yield loss due to lattice misfit stress in MCT and IGBT devices</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>440</div><a href='49/1936086.htm'>Gate insulator characteristics on the bonded thick SOI wafers for automotive IC applications</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>441</div><a href='49/2145312.htm'>Gate insulator process dependent NBTI in SiON p-MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>442</div><a href='49/2441408.htm'>Gate isolation technology for compact poly-CMP embedded flash memories</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>443</div><a href='49/2660409.htm'>Gate I-V characteristics degradation in AlGaN/AlN/GaN HEMTs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>444</div><a href='49/2455545.htm'>Gate last MOSFET with air spacer and self-aligned contacts for dense memories</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>445</div><a href='49/1411128.htm'>Gate layout and bonding pad structure of a RF n-MOSFET for low noise performance</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>446</div><a href='49/2206923.htm'>Gate Layout Improvement Aimed at Testability</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>447</div><a href='49/2908655.htm'>Gate Leakage Analysis of Nano-MOSFETs using Ensemble Full Band Monte Carlo with Quantum Correction</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>448</div><a href='49/2369657.htm'>Gate leakage and its reduction in deep submicron SRAM</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>449</div><a href='49/57699.htm'>Gate Leakage Characteristics for 28 nm HfZrO<sub><italic>x</italic></sub> pMOSFETs After DPN Process Treatment With Different Nitrogen Concentration</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>450</div><a href='49/147928.htm'>Gate leakage current accurate models for nanoscale MOSFET transistors</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>451</div><a href='49/2987792.htm'>Gate leakage current analysis in READ/WRITE/ IDLE states of a SRAM cell</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>452</div><a href='49/2286549.htm'>Gate leakage current in double-gate MOSFETs with Si/SiO<inf>2</inf> interface model from first principle calculations</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>453</div><a href='49/2325704.htm'>Gate leakage current of a double gate N-MOS On (111) silicon - A quantum mechanical study</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>454</div><a href='49/3250625.htm'>Gate leakage current simulation by Boltzmann transport equation and its dependence on the gate oxide thickness</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>455</div><a href='49/2259059.htm'>Gate leakage current simulation for nanoscale NMOSFETs with nitrided gate dielectric by Boltzmann transport equation</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>456</div><a href='49/883278.htm'>Gate leakage currents in MOS field-effect transistors</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>457</div><a href='49/2699587.htm'>Gate leakage currents modeling for oxynitride gate dielectric in double gate MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>458</div><a href='49/3055801.htm'>Gate leakage effects of annealing Lanthanum Oxide on Gallium Nitride</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>459</div><a href='49/2302289.htm'>Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>460</div><a href='49/60291.htm'>Gate Leakage for 28 nm Stacked HfZrO<sub><italic>x</italic></sub> Dielectric of p-Channel MOSFETs After Decoupled Plasma Nitridation Treatment With Annealing Temperatures</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>461</div><a href='49/1381481.htm'>Gate Leakage Impact on Full Open Defects in Interconnect Lines</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>462</div><a href='49/3412728.htm'>Gate leakage in hafnium oxide high-k metal gate nMOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>463</div><a href='49/501476.htm'>Gate leakage in Low Standby Power 16 nm gate length Double-gate MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>464</div><a href='49/57167.htm'>Gate Leakage Mechanisms in AlGaN/GaN and AlInN/GaN HEMTs: Comparison and Modeling</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>465</div><a href='49/435907.htm'>Gate leakage models for device simulation</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>466</div><a href='49/1989607.htm'>Gate Leakage Properties of MOS Devices with Tri-Layer High-k Gate Dielectric</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>467</div><a href='49/3058257.htm'>Gate leakage properties on n-MOSFET with plasma oxidized and nitrided</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>468</div><a href='49/776852.htm'>Gate leakage reduction for scaled devices using transistor stacking</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>469</div><a href='49/1784369.htm'>Gate leakage reduction of AlGaN/GaN MOS-HFETs with HfO<inf>2</inf> prepared by ALD</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>470</div><a href='49/2386185.htm'>Gate Leakage vs. NBTI in Plasma Nitrided Oxides: Characterization, Physical Principles, and Optimization</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>471</div><a href='49/1174489.htm'>Gate Length and Performance Scaling of Undoped-Body Extremely Thin SOI MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>472</div><a href='49/3608302.htm'>Gate Length Dependence of Large-Signal Output Characteristics for the MOSFETs in the Breakdown Region Using X-Parameter Model</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>473</div><a href='49/1266517.htm'>Gate length dependent polysilicon depletion effects</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>474</div><a href='49/757848.htm'>Gate length effect on the RTS noise amplitude in SOI MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>475</div><a href='49/947416.htm'>Gate length electric parameter dependences of ultra-submicrometre delta -doped pseudomorphic HEMTs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>476</div><a href='49/588150.htm'>Gate length impact on UTBOX FBRAM devices</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>477</div><a href='49/1317667.htm'>Gate length scalability of n-MOSFETs down to 30 nm: Comparison between LDD and non-LDD structures</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>478</div><a href='49/2167723.htm'>Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>479</div><a href='49/2931260.htm'>Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>480</div><a href='49/2887071.htm'>Gate length scaling and threshold voltage control of double-gate MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>481</div><a href='49/1385897.htm'>Gate length scaling for Al<sub>0.2</sub>Ga<sub>0.8</sub>N/GaN HJFETs: two-dimensional full band Monte Carlo simulation including polarization effect</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>482</div><a href='49/1921563.htm'>Gate Length Scaling in High fMAX Si/SiGe n-MODFET</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>483</div><a href='49/1317381.htm'>Gate length scaling in high performance InGaP/InGaAs/GaAs pHEMTs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>484</div><a href='49/675587.htm'>Gate length scaling of high-k vertical MOSFET toward 20nm CMOS technology and beyond</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>485</div><a href='49/3678278.htm'>Gate length scaling of Si nanowire FET: A NEGF study</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>486</div><a href='49/2455646.htm'>Gate level fault diagnosis in scan-based BIST</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>487</div><a href='49/899590.htm'>Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>488</div><a href='49/292933.htm'>Gate level optimisation of primitive operator digital filters using a carry save decomposition</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>489</div><a href='49/3335864.htm'>Gate level representation of ECL circuits for fault modeling</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>490</div><a href='49/3219871.htm'>Gate level static power estimation in UDSM processes</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>491</div><a href='49/2302766.htm'>Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>492</div><a href='49/3285218.htm'>Gate Line Edge Roughness Amplitude and Frequency Variation Effects on Intra Die MOS Device Characteristics</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>493</div><a href='49/1532712.htm'>Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>494</div><a href='49/2186505.htm'>Gate load delay computation using analytical models</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>495</div><a href='49/1756050.htm'>Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>496</div><a href='49/3073658.htm'>Gate Material Dependence Of Process Charging Damage In Thin Gate Oxide</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>497</div><a href='49/3483143.htm'>Gate Material Engineered-Trapizoidal Recessed Channel MOSFET (GME-TRC) for Ultra Large Scale Integration (ULSI)</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>498</div><a href='49/3619554.htm'>Gate Material Properties Induced 0.25um SRAM Marginality</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>499</div><a href='49/913124.htm'>Gate Matrix Layout</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>500</div><a href='49/3335699.htm'>Gate matrix layout based on hierarchical net-list representations</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>501</div><a href='49/912057.htm'>Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>502</div><a href='49/3143511.htm'>Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>503</div><a href='49/450574.htm'>Gate Matrix Layout Synthesis with Two-Dimensional Folding</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>504</div><a href='49/285664.htm'>Gate matrix multiple-folding algorithm [for CMOS VLSI]</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>505</div><a href='49/1162819.htm'>Gate matrix partitioning</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>506</div><a href='49/1942185.htm'>Gate matrix partitioning</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>507</div><a href='49/1112622.htm'>Gate metallization$

508

Gate misalignment evaluation method for commercial MOS trapezoidal gate transistors

509

Gate model networks for minimization of multiple-valued logic functions

510

Gate modulation of graphene contacts - on the scaling of graphene FETs

511

GATE Monte Carlo Simulation of a High-Sensitivity and High-Resolution LSO-Based Small Animal PET Camera

512

Gate noise in field effect transistors at moderately high frequencies

513

Gate noise in silicon field-effect transistors

514

Gate operation circuit configuration with a power supply for MOS-gate devices

515

Gate optimization of AlGaN/GaN HEMTs using WSi, Ir, Pd, and Ni Schottky contacts

516

Gate overlap length reduction and shallow junction formation in high-performance fine MOSFETs by ion implantation through thin oxide film

517

Gate oxide breakdown behaviour in a mesa SOI CMOS process

518

Gate Oxide Breakdown in a SOI CMOS Process Usilng MESA Isolatioon

519

Gate oxide breakdown location effect on power amplifier and mixed-signal circuits

520

Gate oxide breakdown model in MOS transistors

521

Gate oxide breakdown on low noise and power amplifier performance

522

Gate oxide breakdown on low noise and power amplifier performance

523

Gate oxide breakdown on nMOSFET cutoff frequency and breakdown resistance

524

Gate oxide breakdown parameter extraction with ground and power supply signature measurements

525

Gate oxide breakdown under Current Limited Constant Voltage Stress

526

Gate oxide charge-to-breakdown correlation to MOSFET hot-electron degradation

527

Gate oxide conductivity of polysilicon thin film transistors

528

Gate oxide damage and charging characterization in a 0.13 μm, triple oxide (1.7/2.2/5.2nm) bulk technology

529

Gate oxide damage due to through the gate implantation in MOS-structures with ultrathin and standard oxides

530

Gate oxide damage measured with a unique GOI structure

531

Gate oxide damage reduction and antenna yield improvement using low temperature preclean for sub-0.25 μm metallization

532

Gate oxide damage reduction using a protective dielectric layer

533

Gate oxide damage: a brief history and a look ahead

534

Gate oxide degradation due to plasma damage related charging while ILD cap oxide deposition - detection, localization and resolution

535

Gate oxide degradation due to trapping of positive charges during Fowler-Nordheim stress at low electron fluence: a rigorous model

536

Gate Oxide Degradation of SiC MOSFET in Switching Conditions

537

Gate oxide effect on wafer level reliability of next generation dram transistors

538

Gate oxide enhancement for whole chip ESD design between different power domains

539

Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress

540

Gate oxide failures due to anomalous stress from HBM ESD testers

541

Gate oxide improvement: statistics and methodology

542

Gate oxide integrity (GOI) of MOS transistors with W/TiN stacked gate

543

Gate oxide integrity and hot-carrier degradation of TaSi2P⁺ polycide gate MOSFETs

544

Gate oxide integrity by initial gate current

545

Gate oxide integrity failure caused by molybdenum contamination introduced in the ion implantation

546

Gate oxide integrity improvement by optimising poly deposition process

547

Gate oxide integrity issue caused by wall-related process drift in plasma etching

548

Gate oxide integrity of MOS/SOS devices

549

Gate oxide integrity of NMOS transistor arrays

550

Gate oxide integrity of thermal oxide grown on high temperature formed Si/sub 0.3/Ge/sub 0.7/

551

Gate oxide integrity on ITOX-SIMOX substrates and influence of test device geometry on characterization

552

Gate oxide integrity on ITOX-SIMOX wafers

553

Gate oxide integrity testing on SOI wafers without test structure fabrication

554

Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits

555

Gate Oxide Leakage and Floating Gate Capacitor Matching Test

556

Gate oxide leakage current analysis and reduction for VLSI circuits

557

Gate oxide multiple soft breakdown (Multi-SBD) impact on CMOS inverter

558

Gate Oxide Process Impact on RNCE for Advanced CMOS Transistors

559

Gate oxide protection and ggNMOSTs in 65 nm

560

Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results

561

Gate Oxide Quality of DRAM Trench Capacitors

562

Gate oxide reliability and deuterated CMOS processing

563

Gate oxide reliability assessment of a SiC MOSFET for high temperature aeronautic applications

564

Gate oxide reliability characterization in the 100ps regime with ultra-fast transmission line pulsing system

565

Gate oxide reliability correlation between test structures and DRAM product chips

566

Gate oxide reliability for nano-scale CMOS

567

Gate Oxide Reliability for Nano-Scale CMOS

568

Gate oxide reliability improvement for CMOS and MEMS monolithic integration

569

Gate oxide reliability improvement for UMOS technology

570

Gate Oxide Reliability in a Sealed Interface Local Oxidation Scheme

571

Gate Oxide Reliability Issues of SiC MOSFETs Under Short-Circuit Operation

572

Gate oxide reliability of 4H-SiC MOS devices

573

Gate oxide reliability of drain-side stresses compared to gate stresses

574

Gate oxide reliability parameters in the range 1.6 to 10 nm

575

Gate oxide reliability under ESD-like pulse stress

576

Gate oxide reliability under ESD-like pulse stress

577

Gate oxide reliability: the use of simulation to quantify important aspects of lifetime projection from TDDB data

578

Gate oxide rupture localization by photon emission microscopy with the combination of Lock-in IR-OBIRCH

579

Gate oxide scaling limits and projection

580

Gate oxide thickness dependence of edge charge trapping in NMOS transistors caused by charge injection under constant-current stress

581

Gate oxide thickness dependence of high-field-induced interface state generation in thin thermal oxides

582

Gate Oxide Thickness Dependence of Hot Carrier Induced Degradation on PMOSFETs

583

Gate oxide thickness dependence of RIE-induced damages on n-channel MOSFET reliability

584

Gate oxide thickness effect on hot carrier reliability in 0.35 /spl mu/m NMOS device

585

Gate oxide thickness measurement using Fowler-Nordheim tunneling

586

Gate oxide thinning at the active device/FOX boundary in submicrometer PBL isolation

587

Gate oxide thinning effects at the edge of shallow trench isolation in the dual gate oxide process

588

Gate Oxide Thinning Limit Influenced by Gate Materials

589

Gate oxide trap characterization under DC and pulse stress

590

Gate Oxide Wear-Out and Breakdown Effects on the Performance of Analog and Digital Circuits

591

Gate oxides in 50 nm devices: thickness uniformity improves projected reliability

592

Gate oxides on 4H-SiC substrates grown or annealed in N₂O/Ar mixture

593

Gate oxynitride grown in nitric oxide (NO)

594

Gate planning during placement for gated clock network

595

Gate polysilicon optimization for deep-submicron MOSFETs

596

Gate postdoping to decouple implant/anneal for gate, source/drain, and extension: maximizing polysilicon gate activation for 0.1 /spl mu/m CMOS technologies

597

Gate power loss of class E amplifier with rectangular wave gate drive

598

Gate prespacers for high density DRAMs

599

Gate propagation delay and logic timing of GaAs integrated circuits measured by electro-optic sampling

600

Gate Protection for CMOS/SOS

601

Gate protection of MIS devices

602

Gate protection of MIS devices

603

Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states

604

Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride and nitrided oxide dielectrics

605

Gate recess engineering of pseudomorphic In_0.30GaAs/GaAs HEMTs

606

Gate recess structure engineering in MESFETs to achieve higher schottky breakdown voltage for switch MMIC applications

607

Gate recessed (GR) MOSFET with selectively halo-doped channel and deep graded source/drain for deep submicron CMOS

608

Gate Recessed Quasi-Normally OFF Al₂O₃/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer

609

Gate recessing of GaN MESFETs using photoelectrochemical wet etching

610

Gate recognition and netlist reduction for switch-level simulation of dynamic bit-level systolic arrays

611

Gate Recognition and Reconstruction for DARPA Robotics Challenge Using Bayesian Classifier Optimized by Mahalanobis Distance

612

Gate reliability comparison of 110 and 100 substrates

613

Gate replacement technique with thick Tox to mitigate leakage with zero delay penalty for DSM CMOS circuit

614

Gate replacement techniques for simultaneous leakage and aging optimization

615

Gate resistance influence on the impedance matching for common gate MOSFET amplifiers

616

Gate resistance modeling of multifin MOS devices

617

Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations

618

Gate Rupture in Ultra-Thin Gate Oxides Irradiated With Heavy Ions

619

Gate rupture in ultra-thin gate oxides irradiated with heavy ions

620

Gate semi-around Si nanowire FET fabricated by conventional CMOS process with very high drivability

621

Gate signal omission to reduce the drive loss of CRM PFC rectifier

622

GATE Simulation of $^{12}{\\rm C}$ Hadrontherapy Treatment Combined With a PET Imaging System for Dose Monitoring: A Feasibility Study

623

GATE Simulation of a BGO Based High Sensitivity Small Animal PET Scanner

624

GATE simulations for small animal SPECT/PET using voxelized phantoms and rotating-head detectors

625

GATE simulations of human and small animal PET for determination of scatter fraction as a function of object size

626

GATE Simulations of Human and Small Animal PET for Determination of Scatter Fraction as a Function of Object Size

627

GATE Simulations of Small Animal SPECT for Determination of Scatter Fraction as a Function of Object Size

628

GATE simulations on multicomputer architectures

629

GATE simulations on multicomputer architectures

630

Gate Sinking Effect of 0. 1 μm InP HEMT MMICs Using Pt/Ti/Pt/Au

631

Gate size dependence of the radiation-produced changes in threshold voltage, mobility, and interface state density in bulk CMOS

632

Gate size optimization for row-based layouts

633

Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits

634

Gate sizing and buffer insertion using economic models for power optimization

635

Gate sizing and device technology selection algorithms for high-performance industrial designs

636

Gate sizing and replication to minimize the effects of virtual ground parasitic resistances in MTCMOS designs

637

Gate sizing and threshold voltage assignment for high performance microprocessor designs

638

Gate sizing and V_t assignment for active-mode leakage power reduction

639

Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation

640

Gate sizing by lagrangian relaxation revisited

641

Gate Sizing by Lagrangian Relaxation Revisited

642

Gate Sizing For Cell Library-Based Designs

643

Gate Sizing for Cell-Library-Based Designs

644

Gate sizing for constrained delay/power/area optimization

645

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

646

Gate sizing for large cell-based designs

647

Gate sizing in MOS digital circuits with linear programming

648

Gate sizing in the presence of gate switching activity and input vector control

649

Gate Sizing Minimizing Delay and Area

650

Gate sizing to eliminate crosstalk induced timing violation

651

Gate sizing to radiation harden combinational logic

652

Gate sizing using a statistical delay model

653

Gate sizing using Geometric Programming

654

Gate sizing using incremental parameterized statistical timing analysis

655

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step

656

Gate sizing: a general purpose optimization approach

657

Gate sizing: finFETs vs 32nm bulk MOSFETs

658

Gate slow transients in GaAs MESFETs-causes, cures, and impact on circuits

659

Gate speed improvement at minimal power dissipation

660

Gate stack etch induced reliability issues in nitrided-based trapping storage cells

661

Gate Stack Optimisation for Advanced CMOS Process

662

Gate stack optimization for 65 nm CMOS low power and high performance platform

663

Gate stack optimization to minimize power consumption in super-lattice fets

664

Gate stack preparation with high-k materials in a cluster tool

665

Gate stack process optimization for TDDB improvement in 28nm high-k/metal gate nMOSFETs

666

Gate stack reliability improvements using controlled ambient processing

667

Gate Stack Reliability of MOSFETs With High-Mobility Channel Materials: Bias Temperature Instability

668

Gate stack resistance and limits to CMOS logic performance

669

Gate Stack Resistance and Limits to CMOS Logic Performance

670

Gate stack technology for nanoscale devices

671

Gate stress study on High Voltage MOSFET for Non-Volatile Memory applications

672

Gate structure optimization of carbon nanotube transistor based infrared detector

673

Gate substrate effect on RF CMOS device noise

674

Gate technologies for AlInAs/InGaAs HEMTs

675

Gate technology and substrate property influence on GaN HEMT switch device performance

676

Gate Technology Contributions to Collapse of Drain Current in AlGaN/GaN Schottky HEMT

677

Gate to channel shorts in PMOS devices: effects on logic gate failures

678

Gate tolerances in sequential circuits

679

Gate Trigger Unit for Voltage Reinjection Multilevel-VSC with Cascaded H-Bridges

680

Gate triggering: a new framework for minimizing glitch power dissipation in static CMOS ICs and its ILP-based optimization

681

Gate tunable MoS2-based thermoelectric devices

682

Gate tunable resonant tunneling in graphene-based heterostructures and device applications

683

Gate tunnel current in an MOS transistors

684

Gate Tunneling Current Fluctuations associated with Random Dopant Effects

685

Gate tunneling current in In/sub 0.53/Ga/sub 0.47/As junction field-effect transistors

686

Gate tunneling current in thin oxide MOSFET

687

Gate tunneling current model of strained Si for scaled NMOSFET

688

Gate Tunneling in Nanowire MOSFETs

689

Gate tunnelling and impact ionisation in sub 100 nm PHEMTs

690

Gate turn-off capability of depletion-mode thyristors

691

Gate turn-off in p-n-p-n devices

692

Gate turn-off thyristor on the basis of the SDB-technique

693

Gate turn-off thyristors with near perfect technology

694

Gate underlaid transistor

695

Gate Unit With Improved Short-Circuit Detection and Turn-Off Capability for 4.5-kV Press-Pack IGBTs Operated at 4-kA Pulse Current

696

Gate usage strategies applied to BiCMOS sea-of-gates arrays

697

Gate voltage contribution to neutron-induced SEB of Trench Gate Fieldstop IGBT

698

Gate Voltage Contribution to Neutron-Induced SEB of Trench Gate Fieldstop IGBT

699

Gate voltage control of stochastic resonance in carbon nanotube field effect transistors

700

Gate voltage dependence of 1/f noise in carbon nanotubes with the different metal contacts

701

Gate voltage dependence of channel length modulation for Ge p-channel MOSFETs

702

Gate voltage dependence of channel length modulation for InGaAs n-channel MOSFETs

703

Gate Voltage Dependence of MOSFET 1/f Noise Statistics

704

Gate voltage dependent model for TDDB lifetime prediction under direct tunneling regime

705

Gate Voltage Influence on the Channel Hot-Carrier Degradation of High- $k$ -Based Devices

706

Gate Voltage Matching Investigation for Low-Power Analog Applications

707

Gate Voltage Pattern Analyze for Short-Circuit Protection in IGBT Inverters

708

Gate voltage swing enhancement of InGaP/ InGaAs pseudomorphic HFET with low-to-high double doping channels

709

Gate waveform effects on high-efficiency PA design: An experimental validation

710

Gate waveform effects on high-efficiency PA design: An experimental validation

711

Gate Width Dependence of Noise Parameters and Scalable Noise Model for HEMTs

712

Gate width optimization of PHEMT MMIC LNA for low power consumption

713

Gate Work Function and Contact Engineering in Nanoscale Vertical Pillar Transistor for DRAM Cell Transistors

714

Gate Work Function Engineering for Nanotube-Based Circuits

715

Gate Workfunction Engineering for Deep Submicron CMOS

716

Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

717

GATE, a Geant4-based simulation platform for PET integrating movement and time management

718

Gate/Source overlapped heterojunction tunnel FET for non-Boolean associative processing with plasticity

719

GATE: a Geant4-based simulation platform for PET and SPECT integrating movement and time management

720

GATE: A Novel Robust Object Tracking Method Using the Particle Filtering and Level Set Method

721

GATE: an environment to support research and development in natural language engineering

722

GATE: game-based testing environment

723

Gateable thin-film transformer

724

Gate-aided drain to field breakdown of high voltage NMOS devices

725

Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires

726

Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack and contact modules

727

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200?S/?m at 50nm Lg using a replacement Fin RMG flow

728

Gate-All-Around Junctionless Nanowire MOSFET With Improved Low-Frequency Noise Behavior

729

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

730

Gate-all-around MOSFETs: lateral ultra-narrow (≤10 nm) fin as channel body

731

Gate-All-Around Nanowire MOSFET With Catalytic Metal Gate For Gas Sensing Applications

732

Gate-All-Around n-MOSFETs With Uniaxial Tensile Strain-Induced Performance Enhancement Scalable to Sub-10-nm Nanowire Diameter

733

Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

734

Gate-all-around OTA´s for rad-hard and high-temperature analog applications

735

Gate-All-Around Poly-Si TFTs With Single-Crystal-Like Nanowire Channels

736

Gate-all-around quantum-wire field-effect transistor with Dopant Segregation at Metal-Semiconductor-Metal heterostucture

737

Gate-all-around Si nanowire array tunnelling FETs with high on-current of 75 µA/µm @ VDD=1.1V

738

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

739

Gate-all-around silicon nanowire MOSFETs and circuits

740

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

741

Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory

742

Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope

743

Gate-All-Around technology: taking advantage of ballistic transport ?

744

Gate-all-around Twin Silicon nanowire SONOS Memory

745

Gate-all-arround single-crystalline silicon nanowire optical sensor

746

Gate-array design. A hierarchical development trend

747

Gate-Array IC Design Tools

748

Gate-array library design using local interconnect

749

Gate-assisted high-Q-factor junction varactor

750

Gate-assisted lateral PNP active load for analog SiGe HBT technology

751

Gate-assisted reverse and forward recovery of high-power GTOs in series resonant DC-link inverters

752

Gate-assisted turn-off effect in TIL-type thyristors

753

Gate-assisted turnoff thyristors

754

Gate-Bias Stress Stability of P-Type SnO Thin-Film Transistors Fabricated by RF-Sputtering

755

Gate-bias-dependent low-frequency oscillations in GaAs MISFET´s

756

Gate-capacitance characteristics of deep-submicron LATID (large-angle-tilt implanted drain) MOSFETs

757

Gate-capacitance extraction from RF C-V measurements [MOS device applications]

758

Gatecard reliability prediction analysis

759

Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET

760

Gate-charge measurements for irradiated n-channel DMOS power transistors

761

Gate-control strategies for snubberless operation of series connected IGBTs

762

Gate-controlled active graphene metamaterials

763

Gate-controlled active graphene metamaterials at terahertz frequencies

764

Gate-controlled All-fiber graphene device and its application to ultrafast fiber laser system

765

Gate-Controlled Bipolar Action in Ultrathin-Body Dynamic-Threshold SOI MOSFET

766

Gate-controlled diodes for ionic concentration measurement

767

Gate-controlled doping in carbon-based FETs

768

Gate-controlled double electron layer tunnelling transistor and single transistor digital logic applications

769

Gate-controlled electromagnetically induced transparency analogue in graphene metamaterials

770

Gate-controlled junction breakdown in stored charge transistors

771

Gate-controlled lateral PNP BJT: characteristics, modeling and circuit applications

772

Gate-controlled negative differential resistance in drain current characteristics of AlGaAs/InGaAs/GaAs pseudomorphic MODFETs

773

Gate-Controlled Photodetector in PIN technology for distance measurements

774

Gate-controlled punch through transistor

775

Gate-controlled rectifying behavior in C70@SWNTs networks

776

Gate-Controlled Reverse Recovery for Characterization of LDMOS Body Diode

777

Gate-controlled Schottky barrier modulation for superior photoresponse of MoS2 field effect transistor

778

Gate-controlled source-to-drain resistance of FET´s

779

Gate-current injection and surface impact ionization in MOSFET´s with a gate induced virtual drain

780

Gate-current-controlled plasma-coupled linear pnpn-devices

781

Gated and STI defined ESD diodes in advanced bulk FinFET technologies

782

Gated Baseline Restorer with Adjustable Asymmetry

783

Gated capacitor store for t.c.m. transmission

784

Gated carbon nanotube emitter with low driving voltage

785

Gated carbon nanotube emitters grown on silicon trench wells with a sidewall spacer for stable vacuum microwave devices

786

Gated carbon nanotube pillar arrays for high current applications

787

Gated Cardiac Scanning Using Limited-Angle Image Reconstruction Technique and Information in the Neighboring Phases

788

Gated cardiac SPECT using different motion models

789

Gated chirps for signal processing and communication engineering

790

Gated Chromium Volcano Emitters

791

Gated classifiers: Boosting under high intra-class variation

792

Gated clock routing for low-power microprocessor design

793

Gated clock routing minimizing the switched capacitance

794

Gated clocks in RT-synthesis and simulation

795

Gated contact chains for process characterization in FinFET technologies

796

Gated current integrator for the beam in the RR barrier buckets

797

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies

798

Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies

799

Gated diamond field emitter array with ultra low operating voltage and high emission current

800

Gated Digital Tomography with a Focal Plane Scanner

801

Gated Diode Design to Mitigate Radiation Damage in X-Ray Imagers

802

Gated diode in breakdown voltage collapse regime — A test vehicle for oxide characterization

803

Gated Diode Investigation of Bias Temperature Instability in High- $\\kappa$ FinFETs

804

Gated direct sequence spread spectrum clocking scheme for multimedia systems

805

Gated dynamic image reconstruction using temporal B-splines

806

Gated Field Emitter Scaling

807

Gated field emitter using carbon nanotubes for vacuum microelectronic devices

808

Gated field-emission cathodes for microwave devices

809

Gated field-emitter arrays for microwave-tube applications

810

Gated FMCW SAR system

811

Gated FMCW SAR System

812

Gated Geiger mode operation and after pulse probability measurement of the InAlAs APD

813

Gated heterodyne coherent anti-Stokes Raman scattering with phase-locked tunable femtosecond pulses

814

Gated in-situ grown carbon nanotube field emitter arrays

815

Gated interferometric imaging of pulsars to detect off-pulse emission

816

Gated laser Doppler flowmetry using a proximity-contact probe

817

Gated lateral bipolar transistors: characteristics, modeling and applications

818

Gated lateral BJT gas sensor for toluene gas detection under room temperature condition

819

Gated Lateral p-i-n Junction Device for Light Sensing

820

Gated micrometer-size electron field emitters

821

Gated Micron-size Electron Field Emitters

822

Gated Phase-Locked Loop Study

823

Gated photodetector based on GaN/AlGaN heterostructure field effect transistor

824

Gated piezoresistive GaN microcantilever as an acoustic transducer

825

Gated p-Si field emitter arrays for sensor applications

826

Gated Real Time Ion Acoustic Wave Studies in Argon and AR-XE Mixture Plasmas

827

Gated reconstruction for PET scan with continuous bed motion

828

Gated Regional Spirometry (GRS)

829

Gated resonant tunnelling devices

830

Gated Sine-Wave Electromagnetic Flowmeter

831

Gated Soft X-ray Images From A Plasma Focus Device

832

Gated SPECT quantification for myocardial thickness, left ventricular volumes and ejection fraction: methodology and phantom validation

833

Gated threshold compensated noncoherent PPM receiver for UWB impulse radio

834

Gated tomographic imaging in ectomography using a dynamic heart phantom

835

Gated tunnel diode with a reactive bias stabilizing network for 60 GHz impulse radio implementations

836

Gated turn-on of four layer switch

837

Gated Twin-Bit (GTB) nonvolatile memory device and its operation

838

Gated UWB pulse signal generation

839

Gated van der Pauw measurements: A powerful tool for probing electron trapping effects in GaN HEMTs

840

Gated X-ray framing camera image of a direct-drive cylindrical implosion

841

Gated, field-emitter arrays and its potential applications

842

Gated-Clock Design of Linear-Feedback Shift Registers

843

Gated-diode amplifiers

844

Gated-diode characterization of the back-channel interface on irradiated SOI wafers

845

Gated-diode study of corner and peripheral leakage current in high-energy neutron irradiated silicon p-n junctions

846

Gate-defined quantum devices realized on an InGaAs/InP heterostructure by incorporating a high-κ dielectric material

847

Gate-defined quantum dot single electron pump

848

Gate-delay fault diagnosis using the inject-and-evaluate paradigm

849

Gate-delay fault test with conventional scan-design

850

Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks

851

Gated-Field Emission Arrays with Single Carbon Nanotubes Grown on Mo Tips

852

Gated-four-probe a-Si:H TFT structure: a new technique to measure the intrinsic performance of a-Si:H TFT

853

Gated-four-probe a-Si:H thin-film transistor structure

854

Gate-dielectric interface effects on low-frequency (1/f) noise in p-MOSFETs with high-K dielectrics

855

Gate-dielectric permitivity and metal-gate work-function tradeoff in L_met=25nm PDSOI device characteristics

856

Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization

857

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

858

Gate-diffusion input (GDI)-a novel power efficient method for digital circuits: a design methodology

859

Gated-pulse stroboscopy for passivated device imaging

860

Gate-drain avalanche breakdown in GaAs power MESFET´s

861

Gate-drain breakdown effects upon the large signal performance of GaAs MESFETs

862

Gate-drain capacitance behaviour of the DMOS power transistor under high current flow

863

Gate-drain capacitance compensation technique for triode MOS transconductors

864

Gate-drain charge analysis for switching in power trench MOSFETs

865

Gate-drive circuit for zero-voltage-switching half-and full-bridge converters

866

Gate-driven 3.3V ESD clamp using 1.8V transistors

867

GATE-Driven Dynamic Wavelength and Bandwidth Allocation for WDM EPONs

868

Gated-scheduling algorithms in packet switching networks

869

Gated-V_dd: a circuit technique to reduce leakage in deep-submicron cache memories

870

Gate-Exhaustive and Cell-Aware pattern sets for industrial designs

871

Gate-Feedback MESFET Grids for Microwave Power Combining

872

Gate-Field Engineering and Source/Drain Diffusion Engineering for High-Performance Si Wire GAA MOSFET and Low-Power Strategy in Sub-30-nm-Channel Regime

873

Gate-field-induced carrier heating in Si MOSFET´s

874

Gate-First $\\hbox {TaN/La}_{2}\\hbox {O}_{3}/ \\hbox {SiO}_{2}/\\hbox {Ge}$ n-MOSFETs Using Laser Annealing

875

Gate-First AlGaN/GaN HEMT Technology for High-Frequency Applications

876

Gate-first Germanium nMOSFET with CVD HfO₂ gate dielectric and silicon surface passivation

877

Gate-first high-k/metal gate DRAM technology for low power and high performance products

878

Gate-first high-k/metal gate stack for advanced CMOS technology

879

Gate-first implant-free InGaAs n-MOSFETs with sub-nm EOT and CMOS-compatible process suitable for VLSI

880

Gate-first integration of Gd-based high-k dielectrics with metal gate electrodes

881

Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High- $k$ /Metal Gates CMOS FinFETs for Multi-

$k$ n-MOSFETs With Deep Sub-nm Equivalent Oxide Thickness (0.58 nm) Fabricated With Sulfur-Implanted Schottky Source/Drain Using a Low-Temperature Pro

884

Gate-first process and EOT-scaling of III-V nanowire-based vertical transistors on Si

885

Gate-First Processed FUSI/HfO2/HfSiOx/Si MOSFETs with EOT=0.5 nm - Interfacial Layer Formation by Cycle-by-Cycle Deposition and Annealing

886

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

887

Gate-Free InGaAs/InP Single-Photon Detector Working at Up to 100 Mcount/s

888

Gate-fringing field effects on high performance in high dielectric LDD spacer MOSFETs

889

Gate-Geometric Recessed Nanoscale $\\hbox {In}_{0.52} \\hbox {Al}_{0.48}\\hbox {As}$ – $\\hbox {In}_{0</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>890</div><a href='49/1951840.htm'>Gate-induced band-to-band tunneling leakage current in LDD MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>891</div><a href='49/3093829.htm'>Gate-induced barrier field effect transistor (GBFET) - a new thin film transistor for active matrix liquid crystal display systems</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>892</div><a href='49/1128084.htm'>Gate-Induced Drain Leakage (GIDL) Improvement for Millisecond Flash Anneal (MFLA) in DRAM Application</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>893</div><a href='49/1149856.htm'>Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n-MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>894</div><a href='49/1471690.htm'>Gate-induced drain leakage current enhanced by plasma charging damage</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>895</div><a href='49/1052689.htm'>Gate-induced drain leakage current in MOS devices</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>896</div><a href='49/3100192.htm'>Gate-induced drain leakage current of MOSFET with junction doping dependence</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>897</div><a href='49/2010585.htm'>Gate-Induced Drain Leakage in Ldd and Fully-Overlapped Ldd Mosfets</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>898</div><a href='49/1051271.htm'>Gate-Induced Drain-Leakage (GIDL) Programming Method for Soft-Programming-Free Operation in Unified RAM (URAM)</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>899</div><a href='49/1420237.htm'>Gate-induced drain-leakage in buried-channel PMOS-a limiting factor in development of low-cost, high-performance 3.3-V, 0.25-μm technology</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>900</div><a href='49/1140369.htm'>Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>901</div><a href='49/873567.htm'>Gate-Induced Image Force Barrier Lowering in Schottky Barrier FETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>902</div><a href='49/1265356.htm'>Gate-Induced Schottky Barrier Lowering Effect in AlGaN/GaN Metal–2DEG Tunnel Junction Field Effect Transistor</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>903</div><a href='49/4025.htm'>Gate-Induced Source Tunneling FET (GISTFET)</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>904</div><a href='49/3559132.htm'>Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>905</div><a href='49/1108892.htm'>Gate-Interconnection Minimization of Switching Networks Using Negative Gates</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>906</div><a href='49/1623468.htm'>Gatekeeper: An untethered, persistent, station-keeping gateway buoy</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>907</div><a href='49/1383671.htm'>Gatekeeping Economics</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>908</div><a href='49/449932.htm'>Gatekeeping in Virtual Communities: On Politics of Power in Cyberspace</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>909</div><a href='49/3088409.htm'>Gate-last integration on planar FDSOI MOSFET: Impact of mechanical boosters and channel orientations</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>910</div><a href='49/414457.htm'>Gate-last MISFET structures and process for high-k and metal gate MISFETs characterization</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>911</div><a href='49/549685.htm'>Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>912</div><a href='49/408425.htm'>Gate-leakage estimation and minimization in CMOS combinatorial circuits</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>913</div><a href='49/3464340.htm'>Gate-leakage model of Ge MOS capacitor with high-k gate dielectric</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>914</div><a href='49/1045522.htm'>Gate-Length and Drain-Bias Dependence of Band-to-Band Tunneling-Induced Drain Leakage in Irradiated Fully Depleted SOI Devices</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>915</div><a href='49/954711.htm'>Gate-length biasing for runtime-leakage control</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>916</div><a href='49/2025656.htm'>Gate-length dependence of bulk generation lifetime and surface generation velocity measurement in high-resistivity silicon using gated diodes</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>917</div><a href='49/1179023.htm'>Gate-length dependence of DC and microwave properties of submicrometer In/sub 0.53/Ga/sub 0.47/As HIGFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>918</div><a href='49/1107985.htm'>Gate-length dependence of the speed of SSI circuits using submicrometer selectively doped heterostructure transistor technology</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>919</div><a href='49/1486634.htm'>Gate-Length Scaling of Ultrashort Metamorphic High-Electron Mobility Transistors With Asymmetrically Recessed Gate Contacts for Millimeter- and Submillimeter-Wave Applications</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>920</div><a href='49/1158675.htm'>Gate-Length-Dependent Strain Effect in n- and p-Channel FinFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>921</div><a href='49/3529260.htm'>Gateless depletion mode field effect transistor for macromolecule sensing</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>922</div><a href='49/999040.htm'>Gateless synchronous counters with D flip-flops</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>923</div><a href='49/1588628.htm'>Gateless-FET undoped AlGaN/GaN HEMT structure for liquid-phase sensor</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>924</div><a href='49/1890179.htm'>Gate-level aged timing simulation methodology for hot-carrier reliability assurance</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>925</div><a href='49/2919432.htm'>Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>926</div><a href='49/523588.htm'>Gate-level characterization: Foundations and hardware security applications</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>927</div><a href='49/3564581.htm'>Gate-level commercial microelectronics verification with standard cell recognition</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>928</div><a href='49/2506098.htm'>Gate-level current waveform simulation of CMOS integrated circuits</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>929</div><a href='49/2371421.htm'>Gate-level design diagnosis using a learning-based search strategy</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>930</div><a href='49/3016883.htm'>Gate-level design exploiting dual supply voltages for power-driven applications</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>931</div><a href='49/2546742.htm'>Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>932</div><a href='49/2154529.htm'>Gate-level dual-threshold total power optimization methodology (GDTPOM) principle for designing high-speed low-power SOC applications</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>933</div><a href='49/2350970.htm'>Gate-Level Evolutionary Development Using Cellular Automata</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>934</div><a href='49/3431946.htm'>Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>935</div><a href='49/2110918.htm'>Gate-level fault diagnosis for scan-based VLSI environment</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>936</div><a href='49/1439704.htm'>Gate-Level Information-Flow Tracking for Secure Architectures</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>937</div><a href='49/430237.htm'>Gate-level mitigation techniques for neutron-induced soft error rate</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>938</div><a href='49/597211.htm'>Gate-level modeling for CMOS circuit simulation with ultimate FinFETs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>939</div><a href='49/1319895.htm'>Gate-level modeling of leakage current failure induced by total dose for the generation of worst-case test vectors</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>940</div><a href='49/2100435.htm'>Gate-level modelling and verification of asynchronous circuits using CSPM and FDR</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>941</div><a href='49/2028444.htm'>Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>942</div><a href='49/1638856.htm'>Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>943</div><a href='49/1522836.htm'>Gate-level power and current simulation of CMOS integrated circuits</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>944</div><a href='49/1453218.htm'>Gate-level power estimation using tagged probabilistic simulation</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>945</div><a href='49/2316918.htm'>Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>946</div><a href='49/1074529.htm'>Gate-Level Redundancy: A New Design-for-Reliability Paradigm for Nanotechnologies</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>947</div><a href='49/3798561.htm'>Gate-Level Simulation</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>948</div><a href='49/1665962.htm'>Gate-Level Simulation of a FPGA-Based PMSM Drive Sensorless Control</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>949</div><a href='49/1745194.htm'>Gate-level simulation of CMOS circuits using the IDDM model</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>950</div><a href='49/2996961.htm'>Gate-level simulation of digital circuits using multi-valued Boolean algebras</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>951</div><a href='49/3399212.htm'>Gate-level simulation of quantum circuits</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>952</div><a href='49/2509300.htm'>Gate-level synthesis for low-power using new transformations</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>953</div><a href='49/2437905.htm'>Gate-level synthesis of Boolean functions using binary multiplexers and genetic programming</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>954</div><a href='49/2092272.htm'>Gate-level synthesis of Boolean functions using information theory concepts</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>955</div><a href='49/1295357.htm'>Gate-level voltage scaling for low-power design using multiple supply voltages</a></div> <div class='valueDiv recordListRow'><div class='rowCountCircle'>956</div><a href='49/2524879.htm'>GateMaker: a transistor to gate level model extractor for simulation, automatic test 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