بر اساس عنوان

1
Test beam results from the CMS electromagnetic calorimeter
2
Test beam results of a low-pressure micro-strip gas chamber with a secondary-electron emitter
3
Test Beam Results Of A Uranium/TMP Hadronic And Electromagnetic Calorimeter
4
Test beam results of the CALICE silicon-tungsten electromagnetic calorimeter
5
Test beam results of the GE1/1 prototype for a future upgrade of the CMS high-η muon system
6
Test Beam Studies of a Silicon Microstrip Vertex Detector
7
Test beam study of a short drift GEM tracking detector
8
Test bed computer network centralized core and distributed inner core simulation protocol organization, development, and performance evaluation realizing a neural network forecaster
9
Test bed evaluation of future power distribution systems with renewable resources
10
Test Bed for a Smart Millimetre Wave Radar Sensor
11
Test Bed for Assessment of CNO and EW Against Emulated Wireless Ad Hoc Networks
12
Test bed for electromagnetic compatibility tests on effect of ultra-short pulsed electromagnetics
13
Test bed for low-cost measurement of AM/AM and AM/PM effects in RF PAs based on FPGA
14
Test bed for number plate recognition applications
15
Test bed for Remote Environmental Monitoring in Northwestern China
16
Test Bed for Studying Real-Time Simulation and Control for Shipboard Power Systems
17
Test Bed for Superconducting Materials
18
Test bed for time jitter studies of laser-triggered gas-discharge switches
19
Test bed for wireless sensor networks using XMesh networking protocol
20
Test bed implementation of 380V DC distribution system using isolated bidirectional power converters
21
Test bed of control system using multimedia technology at PLS
22
Test bed system to evaluate the efficiency of variable speed drives under varying load conditions
23
Test bed to teach power quality applying the b-learning methodology
24
Test Bed trials for local CWDM network
25
Test bed with force-measuring crank for static and dynamic investigations on cycling by means of functional electrical stimulation
26
Test bed: 4G LTE pertinence for power distribution networks
27
Test before touch
28
Test Before Touch - Easier Said Than Done
29
Test bench and quality measures for non-intrusive load monitoring algorithms
30
Test bench automation to overcome verification challenge of SOC Interconnect
31
Test bench development for acquisition module FPGA of Ultrasonic flow meter
32
Test Bench for a high performance PSM drive system for a nautical application
33
Test bench for active ageing of power modules reproducing constraints close to automotive driving conditions
34
Test bench for converters reliability studies for EV and HEV electrical vehicle applications
35
Test bench for digital beamforming performances characterisation
36
Test bench for emulating electric-drive vehicle systems using equivalent vehicle rotational inertia
37
Test bench for flow cavitational processing of liquid media
38
Test bench for fractional horse power single phase induction motors using virtual instrumentation
39
Test bench for grid code simulations for multi-MW wind turbines
40
Test Bench for Grid Code Simulations for Multi-MW Wind Turbines, Design and Control
41
Test bench for helicopter electro mechanical actuation system validation: Design and validation of dedicated test bench for aeronautical electromechanical actuators
42
Test Bench for HID-MH Lamps Operating in High Frequency
43
Test bench for industrial burners: a diagnostic study for combustion control and process regulation
44
Test bench for investigation of awkward shaped signals influence on radioelectronic equipment
45
Test bench for measuring the electrical properties of commercial thermoelectric modules
46
Test bench for multi-MW grid side wind power converter
47
Test Bench for Process Control Valves.
48
Test bench for routing optimization algorithms in Proxy Mobile IPv6 environments
49
Test bench for self-healing functionalities applied on distribution network with distributed generators
50
Test bench for signal processing modules examination and efficiency rating
51
Test bench for switched reluctance motor drives
52
Test bench for the characterisation of experimental low voltage IGCTs
53
Test bench for the evaluation of GSM-R operation in the presence of electric arc interference
54
Test bench for the simulation of a hybrid power train
55
Test bench Linux-based platform for power quality experiments
56
Test bench model and algorithms for multi-sources light electric vehicle energy management system
57
Test bench modeling and characterization for fine pitch wafer level packaged devices
58
Test Bench of Hybrid Electric Vehicle with the Super Capacitor based Energy Storage
59
Test bench of UAV navigation equipment
60
Test Bench Realization and Application of Specific Working Cycles for the Characterization of Wheelchair Electrical Drives
61
Test Bench System Research for Aircraft Flexible Shaft Assembly
62
Test bench to emulate an electric vehicle through equivalent inertia and machine dc
63
Test Benchmarks -- what is the question?
64
Test blueprint: an effective visual support for test coverage
65
Test Blueprints - Exposing Side Effects in Execution Traces to Support Writing Unit Tests
66
Test board design and measurement techniques for high-frequency fully-differential CMOS OTAs
67
Test board for power FET´s nonliner model extraction
68
Test buffer with extended common mode input voltage
69
Test bus assignment, sizing, and partitioning for system-on-chip
70
Test bus sizing for system-on-a-chip
71
Test by Contract for UML-Based Software Component Testing
72
Test by distributed monitoring
73
Test Calculation for Logic and Delay Faults in Digital Circuits
74
Test calculation for logic and short-circuit faults in digital circuits
75
Test campaign of the IOV (In Orbit Validation) Galileo system navigation antenna for Global Positioning
76
Test Card `M´-do you get the picture?
77
Test case analytics: Mining test case traces to improve risk-driven testing
78
Test Case Automate Generation from UML Sequence Diagram and OCL Expression
79
Test Case Coverage Analysis of UOF/OOXML Translator Based on Path
80
Test case design based on Z and the classification-tree method
81
Test Case Generation and Prioritization from UML Models
82
Test case generation and reduction by automated input-output analysis
83
Test case generation approach for industrial automation systems
84
Test case generation based on adaptive genetic algorithm
85
Test case generation based on formal specifications in Estelle
86
Test Case Generation Based on Invariant Extraction
87
Test case generation based on time constraints
88
Test case generation by means of UML sequence diagrams and labeled transition systems
89
Test case generation by OCL mutation and constraint solving
90
Test Case Generation by Simulating Requirements Analysis Model
91
Test case generation for automotive applications
92
Test Case Generation for Collaborative Real-time Editing Tools
93
Test Case Generation for Critical Systems through a Collaborative Web-Based Tool
94
Test case generation for event driven systems using 4-way input test strategy
95
Test case generation for flexible real-time control systems
96
Test case generation for information systems using reverse engineering techniques
97
Test Case Generation for Modified Code Using a Variant of Particle Swarm Optimization (PSO) Algorithm
98
Test Case Generation for Non-functional and Functional Testing of Services
99
Test Case Generation for Object-Oriented Systems: A Review
100
Test case generation for use case dependency fault detection
101
Test Case Generation from Cause-Effect Graph Based on Model Transformation
102
Test Case Generation from Mutants Using Model Checking Techniques
103
Test Case Generation from UML State Machine Diagram: A Survey
104
Test Case Generation from UML Subactivity and Activity Diagram
105
Test Case Generation Method for BPEL-Based Testing
106
Test case generation of a protocol by a fault coverage analysis
107
Test Case Generation of Concurrent Programs Based on Event Graph
108
Test Case Generation Technique Based on Extended Coverability Trees
109
Test Case Generation Using Model Checking for Software Components Deployed into New  Environments
110
Test Case Generation Using PDA
111
Test case generation using stochastic automata networks: quantitative analysis
112
Test Case Management System (TCMS)
113
Test Case Mutation in Hybrid State Space for Reduction of No-Fault-Found Test Results in the Industrial Automation Domain
114
Test Case Prioritization Based on Analysis of Program Structure
115
Test case prioritization based on data reuse an experimental study
116
Test Case Prioritization Based on Information Retrieval Concepts
117
Test Case Prioritization Based on Varying Testing Requirement Priorities and Test Case Costs
118
Test Case Prioritization Due to Database Changes in Web Applications
119
Test Case Prioritization for Audit Testing of Evolving Web Services Using Information Retrieval Techniques
120
Test Case Prioritization for Black Box Testing
121
Test Case Prioritization for Continuous Regression Testing: An Industrial Case Study
122
Test Case Prioritization for Multiple Processing Queues
123
Test case prioritization for regression testing based on ant colony optimization
124
Test case prioritization for regression testing based on fault dependency
125
Test Case Prioritization for Regression Testing Based on Function Call Path
126
Test Case Prioritization for Web Service Regression Testing
127
Test case prioritization incorporating ordered sequence of program elements
128
Test Case Prioritization Technique Based on Genetic Algorithm
129
Test case prioritization techniques “an empirical study”
130
Test case prioritization using multi objective particle swarm optimizer
131
Test Case Prioritization Using Relevant Slices
132
Test Case Prioritization Using Requirements-Based Clustering
133
Test case prioritization with improved genetic algorithm
134
Test case prioritization with textual comparison metrics
135
Test case prioritization: a family of empirical studies
136
Test case prioritization: An approach based on modified ant colony optimization (m-ACO)
137
Test case prioritization: an empirical study
138
Test case quality in test driven development: A study design and a pilot experiment
139
Test Case Reduction Based on Program Invariant and Genetic Algorithm
140
Test Case Reduction Technique for BPEL-based Testing
141
Test Case Reusability Metrics Model
142
Test Case Reuse Based on Ontology
143
Test Case Reuse in Enterprise Software Implementation -- An Experience Report
144
Test case selection and prioritization using cuckoos search algorithm
145
Test Case Selection Based on Path Condtions of Symbolic Execution
146
Test case selection for networked production systems
147
Test case selection for regression testing of applications using web services based on WSDL specification changes
148
Test Case Selection Method for Emergency Changes
149
Test case selection technique for regression testing using differential control flow graphs
150
Test Case-Aware Combinatorial Interaction Testing
151
Test cases for unit commitment and hydrothermal scheduling problems
152
Test cases for wind power plant dynamic models on real-time digital simulator
153
Test Cases Generation for Embedded Real-Time Software Based on Extended UML
154
Test Cases Generation from UML Activity Diagrams
155
Test cases generation from UML state diagrams
156
Test cases prioritization for software regression testing using analytic hierarchy process
157
Test cases: emergent generalizations in the Athena and the Rumelhart´s neural net models
158
Test cell for electric strength of rubber-epoxy interfaces
159
Test cell for interfacial electric strength testing
160
Test cells for electromagnetic characterization of materials
161
Test cells for evaluation of low currents and capacitances CMOS devices
162
Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau
163
Test challenges for 3D circuits
164
Test Challenges for 3D Integrated Circuits
165
Test challenges for 3D integration (an invited paper for CICC 2011)
166
Test challenges for 3D-SICs: All the old, most of the recent, and then some new!
167
Test challenges for deep sub-micron technologies
168
Test challenges for SONET/SDH physical layer OC3 devices and beyond
169
Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track
170
Test challenges in nanometer technologies
171
Test Characterisation of a H2 PEM Fuel Cell
172
Test chip and data considerations for MOS parameter extraction
173
Test chip and infrastructure IP solutions to improve the back-end process during all phases from a new technology development to manufacturing
174
Test chip based approach to automated diagnosis of CMOS yield problems
175
Test chip characterization of X architecture diagonal lines for SoC design
176
Test Chip design for study of CDM related failures in SoC designs
177
Test chip development to support standardization efforts
178
Test Chip Electrical Measurements with Model Correlation
179
Test chip experiments at stanford CRC
180
Test chip fabrication with extreme ultraviolet lithography for high-volume manufacturing
181
Test chip for bump bond yield evaluation in high density flip chip technologies
182
Test Chip for Characterization of Mechanical Stress Caused by Packaging Processes
183
Test chip for detecting thin film cracking induced by fast temperature cycling and electromigration in multilevel interconnect systems
184
Test chip for electrical linewidth of copper-interconnect features and related parameters
185
Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design
186
Test chip for the development and evaluation of sensors for measuring stress in metal interconnects
187
Test chip for the development and evaluation of test structures for measuring stress in metal interconnect
188
Test chip for the evaluation of surface-diffusion phenomena in sputtered aluminum planarization processes
189
Test Chip to Evaluate Measurement Methods for Small Capacitances
190
Test chips for advanced packaging
191
Test chips for die stress characterization using arrays of CMOS sensors
192
Test chips for evaluating strong phase shift lithography
193
Test chips for the evaluation of the performance of IC packaging and interconnection technologies
194
Test Chips in LSI Reliability Assurance
195
Test chips, test systems and thermal test data for multichip modules in the ESPRIT-APACHIP project
196
Test chips, test systems, and thermal test data for multichip modules in the ESPRIT-APACHIP project
197
Test chirp signal generation using spectral warping
198
Test circuit for accurate measurement of setup/hold and access time of memories
199
Test circuit for CMOS lead open detection by supply current testing under AC electric field application
200
Test Circuit for Evaluation of Breaking Capacity of Motor Starters
201
Test circuit for measuring pulse widths of single-event transients causing soft errors
202
Test Circuit for Measuring Pulse Widths of Single-Event Transients Causing Soft Errors
203
Test circuit for measuring single-event-induced charge sharing in deep-submicron technologies
204
Test Circuit for Study of CMOS Process Variation by Measurement of Analog Characteristics
205
Test Circuit Structures For Characterizing The Effects Of Localized Hot-carrier-induced Charge In VLSI Switching Circuits
206
Test circuits and diagnosis methods of HV SF6 and minimum-oil circuit breakers at capacitive currents switching
207
Test Circuits for Capacitance Switching Devices [includes discussion]
208
Test circuits for characterizing power transistors in ZVS and ZCS circuits
209
Test circuits for deep sub-micron surface acoustic wave devices
210
Test circuits for extracting sub-100nm MOSFET technology variations with the MOSFET model HiSIM
211
Test circuits for fast and reliable assessment of CDM robustness of I/O stages
212
Test circuits for substrate noise evaluation in CMOS digital ICs
213
Test circuits for verification of power device models
214
Test City metaphor as support for visual testcase analysis within integration test domain
215
Test clock domain optimization for peak power supply noise reduction during scan
216
Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering
217
Test CMOS/SOS RAM for transient radiation upset comparative research and failure analysis
218
Test Code Quality and Its Relation to Issue Handling Performance
219
Test codes for electrical machines
220
Test Coil for the Development of a Compact 3 T {\\rm MgB}_{2} Magnet
221
Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks
222
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks
223
Test compaction by test cube merging for four-way bridging faults
224
Test compaction by using linear-matrix driven scan chains
225
Test compaction for at-speed testing of scan circuits based on nonscan test. sequences and removal of transfer sequences
226
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data
227
Test compaction for sequential circuits
228
Test compaction for synchronous sequential circuits by test sequence recycling
229
Test Compaction for Transition Faults under Transparent-Scan
230
Test compaction in a parallel access scan environment
231
Test compaction methods for transition faults under transparent-scan
232
Test Complement Exclusion: Guarantees from Dynamic Analysis
233
Test component assignment in a performance testing environment
234
Test compression - real issues and matching solutions
235
Test Compression / Decompression Based on JPEG VLC Algorithm
236
Test compression and hardware decompression for scan-based SoCs
237
Test compression and logic BIST at your fingertips
238
Test Compression Based on Lossy Image Encoding
239
Test compression for circuits with multiple scan chains
240
Test Compression for Dynamically Reconfigurable Processors
241
Test Compression for FPGAs
242
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
243
Test Compression Improvement with EDT Channel Sharing in SoC Designs
244
Test compression saves bits, cycles, and money
245
Test concept and experimental validation of the use of built-in-test to simplify conducted susceptibility testing of advanced technology integrated circuits and printed circuit boards
246
Test concepts applied to French Army equipment in the field from 1990 to 2000
247
Test Conditions and Error Concealment for SVC Based on RTP Encapsulation
248
Test conditions discussion of particle impact noise detection for space relay
249
Test confessions: A study of testing practices for plug-in systems
250
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study
251
Test Configurations for Diagnosing Faulty Links in NoC Switches
252
Test configurations to enhance the testability of sequential circuits
253
Test connections - tying application to process
254
Test consideration for nanometer scale CMOS circuits
255
Test consideration for nanometer-scale CMOS circuits
256
Test Considerations about the Structured ASIC Paradigm
257
Test considerations for BiCMOS logic families
258
Test Considerations for Gate Oxide Shorts in CMOS ICs
259
Test considerations for jitter tolerance of wireline receivers
260
Test considerations for mixed analog and digital ASICs
261
Test Construction for Cognitive Diagnosis
262
Test construction tool based on Interoperability standards
263
Test consulting system for switching systems
264
Test control for secure scan designs
265
Test control of TAM-bus: a solution for testing SoC
266
Test Control via DOS Middleware Instrumentation
267
Test control&communication of hierarchical design-for-testability for testing dynamically reconfigurable computer
268
Test Controller Synthesis Constrained by Circuit Testability Analysis
269
Test Cost Analysis for 3D Die-to-Wafer Stacking
270
Test cost and test power conflicts: EDA perspective
271
Test cost efficiency exploration for CMT processors
272
Test cost minimization for hybrid BIST
273
Test cost minimization through adaptive test development
274
Test cost optimization technique for the pre-bond test of 3D ICs
275
Test cost reduction by at-speed BISR for embedded DRAMs
276
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing
277
Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data
278
Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling
279
Test cost reduction for SOCs using TAMs and Lagrange multipliers
280
Test cost reduction for the AMD™ Athlon processor using test partitioning
281
Test cost reduction through a reconfigurable scan architecture
282
Test cost reduction through compression
283
Test cost reduction through performance prediction using virtual probe
284
Test cost reduction using partitioned grid random access scan
285
Test cost saving and challenges in the implementation of ×6 and ×8 parallel testing on freescale 16-bit HCS12 microcontroller product family
286
Test cost/coverage tradeoffs in complex telecommunication circuits
287
Test counting: a tool for VLSI testing
288
Test coverage analysis based on program slicing
289
Test Coverage Analysis of UML Activity Diagrams for Interactive Systems
290
Test Coverage Analysis of UML State Machines
291
Test coverage and post-verification defects: A multiple case study
292
Test coverage dependent software reliability estimation by the HGD model
293
Test coverage for collaborative workflow application based on Petri Net
294
Test Coverage Metric for Two-Staged Language with Abstract Interpretation
295
Test coverage models for system test?
296
Test Coverage of Data-Centric Dynamic Compositions in Service-Based Systems
297
Test coverage of the safety instrumented system
298
Test Coverage Optimization for Large Code Problems
299
Test coverage: what does it mean when a board test passes?
300
Test Criteria and Methodology for Evaluation of Coal Mine Monitoring and Control Systems
301
Test criteria for context-free grammars
302
Test criteria for model-checking-assisted test case generation: A computational study
303
Test CSRC´s Ability to Select Firms for IPO and Public Offering
304
Test CSRC´s Ability to Select Private-Owned Enterprises for IPO
305
Test cycle count reduction in a parallel scan BIST environment
306
Test cycle power optimization for scan-based designs
307
Test cycles for the characterization of electrical drives devoted to wheelchair applications
308
Test data adequacy measurement
309
Test data analytics — Exploring spatial and test-item correlations in production test data
310
Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures
311
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture
312
Test Data Combination Strategy for Effective Test Suite Generation
313
Test data compression
314
Test data compression and compaction for embedded test of nanometer technology designs
315
Test data compression and decompression based on internal scan chains and Golomb coding
316
Test data compression and TAM design
317
Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes
318
Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture
319
Test data compression and test time reduction using an embedded microprocessor
320
Test data compression based on clustered random access scan
321
Test data compression based on input-output dependence
322
Test data compression based on output dependence
323
Test data compression based on reuse and bit-flipping of parts of dictionary entries
324
Test data compression based on the reuse of parts of the dictionary entries
325
Test data compression based on Variable Prefix Dual-Run-Length Code
326
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability
327
Test Data Compression by Spilt-VIHC (SVIHC)
328
Test data compression for any quantum Boolean circuits
329
Test data compression for IP embedded cores using selective encoding of scan slices
330
Test data compression for system-on-a-chip using extended frequency-directed run-length code
331
Test data compression for system-on-a-chip using Golomb codes
332
Test Data Compression of 100x for Scan-Based BIST
333
Test data compression strategy while using hybrid-BIST methodology
334
Test data compression technique for embedded cores using virtual scan chains
335
Test data compression technique using selective don´t-care identification
336
Test data compression using dictionaries with fixed-length indices [SOC testing]
337
Test data compression using don´t-care identification and statistical encoding
338
Test data compression using don´t-care identification and statistical encoding [logic testing]
339
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods
340
Test data compression using extended frequency-directed run length code based on compatibility
341
Test data compression using Hamming Encoder and Decoder for system on chip (SOC) testing
342
Test Data Compression Using Selective Encoding of Scan Slices
343
Test Data Compression with Partial LFSR-Reseeding
344
Test data compression: the system integrator´s perspective
345
Test data decompression for multiple scan designs with boundary scan
346
Test data design of a program
347
Test Data Generation Algorithm of Combinatorial Testing Based on Differential Evolution
348
Test data generation based on binary search for class-level testing
349
Test Data Generation Considering Data Dependence
350
Test Data Generation for C Programs with String-Handling Functions
351
Test Data Generation for Derived Types in C Program
352
Test Data Generation for Multiple Paths Based on Local Evolution
353
Test data generation framework for Automatic Programming Assessment
354
Test data generation from Hibernate constraints
355
Test Data Generation from UML State Machine Diagrams using GAs
356
Test Data Generation Using Annealing Immune Genetic Algorithm
357
Test data manipulation techniques for energy-frugal, rapid scan test
358
Test Data Provision for ERP Systems
359
Test Data Reduction
360
Test data reduction based on dominance relations of target statements
361
Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code
362
Test Data Selection and Quality Estimation Based on the Concept of Essential Branches for Path Testing
363
Test data selection criteria for (software) integration testing
364
Test data truncation for test quality maximisation under ATE memory depth constraint
365
Test Data Verification - Not Just the Final Step for Test Data before Release for Production Testing
366
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing
367
Test data volume for multiscan-based designs through single/sequence mixed encoding
368
Test data volume minimization using double hamming distance reordering with mixed RL-Huffman based compression scheme for system-on-chip
369
Test data volume reduction by test data realignment
370
Test Database Analysis - Inferences from a Disposition Tree
371
Test deployment of the PolarBear experiment
372
Test derivation for semantically described IoT services
373
Test design compilers complement top down ASIC design
374
Test Detection by Nuclear Chemistry
375
Test development and deployment tool-set for mixed-signal and digital devices
376
Test development for a third-version ColdFire microprocessor
377
Test development for second-generation ColdFire microprocessors
378
Test development tools framework
379
Test device for motor vehicle breaking system
380
Test device for radiated immunity tests
381
Test device of power frequency voltage imposed with impulse voltage
382
Test devices unified access model in spacecraft automatic test
383
Test diagram generation: A practical application of the ATML standards
384
Test Dipole Magnets for the Tristan Superconducting Proton Ring
385
Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming
386
Test document [Welcome to REDEC 2014]
387
Test driven design
388
Test Driven Design Challenges for Faster Product Development
389
Test Driven Design Methodology for Component-Based System
390
Test driven development and the scientific method
391
Test driven development contribution in universities in producing quality software: A systematic review
392
Test driven development for device drivers and rapid hardware prototyping
393
Test Driven domain modelling
394
Test Economics - What can a Board/System Test Engineer do to Influence Supply Operation Metrics
395
Test economics for homogeneous manycore systems
396
Test economics for multi-site test with modern cost reduction techniques
397
Test economics in the 2lst Century
398
Test education for students and industry at Brunel University
399
Test education for VLSI systems design engineers
400
Test Education in the Global Economy
401
Test education: a CASS perspective
402
Test effectiveness evaluation through analysis of readily-available tester data
403
Test effectiveness index: Integrating product metrics with process metrics
404
Test effectiveness metrics for CMOS faults
405
Test Efficiency Analysis and Improvement of SOC Test Platforms
406
Test efficiency analysis of random self-test of sequential circuits
407
Test effort estimation in regression testing
408
Test Effort Estimation Models Based on Test Specifications
409
Test effort optimization by prediction and ranking of fault-prone software modules
410
Test electronics for a multi-gbps optical packet switching network
411
Test embedding with discrete logarithms
412
Test embedding with discrete logarithms
413
Test Enabled Process Tuning for Adaptive Baseband OFDM Processor
414
Test Encoding for Extreme Response Compaction
415
Test engineering education in Europe: the EuNICE-Test project
416
Test engineering education is rational, feasible, and relevant
417
Test engineering education: a guide to a successful curriculum
418
Test Engineering for CMOS Gate Arrays with the CAD-System VENUS 1
419
Test engineers role in QML
420
Test engines produce electricity
421
Test enrichment for path delay faults using multiple sets of target faults
422
Test enrichment for path delay faults using multiple sets of target faults
423
Test entrance´s selection for fault diagnosis of a self-propelled fire control system based on TC-SVM
424
Test Environment Design for Wireless Vehicle Communications
425
Test environment for a novel medium voltage impedance measurement unit
426
Test environment for Bluetooth Baseband integrated circuit development
427
Test environment for characterization of a nanoscale sensor system consisting of fluid flow sensors based on the Thermal-Time-of-Flight (TToF) principle and absolute pressure sensors
428
Test environment for QoS testing of VoIP over LTE
429
Test environment for the evaluation of IEEE 1588 solutions including high precission PPS output performance measurements
430
Test environment for VSN routing algorithms using mobile robot
431
Test equating and model application
432
Test equations for validation of critical measurements and critical sets at power system state estimation
433
Test equipment accuracy?requirements of the 15th edition
434
Test Equipment and Techniques for Airborne-Radar Field Maintenance
435
Test equipment correlation: a statistical approach
436
Test Equipment for DAC´s Performance Assessment: Design and Characterization
437
Test equipment for digital channel analysis and its application in digital mobile radio
438
Test equipment for distribution automation
439
Test equipment for television transmission circuits
440
Test equipment for television transmission circuits
441
Test equipment for the installation engineer
442
Test equipment for the measurement of static and dynamic resolutions of television cameras
443
Test Equipment for the Time and Frequency Domain Measurement of SAW Filters
444
Test equipment from HP
445
Test equipment refresh for high reliability, mission critical hardware
446
Test equipment research and development studied at NYU
447
Test Equipment Selection and Deployment of Materiel System Based on Grey Situation Decision
448
Test equipment-a call for standardization
449
Test error bounds for classifiers: A survey of old and new results
450
Test evaluation and data on defect-oriented BIST architecture for high-speed PLL
451
Test evaluation for complex mixed-signal ICs by introducing layout dependent faults
452
Test evaluation for life cycle investigation of Wayside lightning arrester in electric railway
453
Test everything everywhere [Design & Production Instrumentation]
454
Test evolution: RADARSAT-1 to RADARSAT-2
455
Test Execution Control Tool: automating testing in spacecraft integration and test environments
456
Test execution method based on TTCN´s operational semantics
457
Test executive features for improved TPS debug
458
Test experience using marine radiobeacons for DGPS communications
459
Test experience with multiterminal HVDC load flow and stability programs
460
Test exploration and validation using transaction level models
461
Test fabrication of a copper beam duct for the KEK B-factory
462
Test facilities and safety regulations for rooftop mounted and grid-connected PV systems
463
Test facilities for electronic industry
464
Test facilities for future linear colliders
465
Test facilities study for the NASA advanced CNS architectures and systems technologies project
466
Test Facility and Experimental Studies of Monocrystal HTS Pellets
467
Test facility for a hybrid fuel cell electric vehicle
468
Test facility for control system validation in electric industrial plants
469
Test facility for high pressure plasmas
470
Test facility for investigations of high-current superconductor samples [for fusion machines]
471
Test Facility for Relativistic Beam Pickups
472
Test facility for SHF (C and Ku-band) satellite communications
473
Test facility of multi-factors aging for stator bars insulation of generator and design of specimens
474
Test facility of proton beam utilization of PEFP at SNU-AMS tandem accelerator
475
Test facility uncertainty calculation methodology and rationale
476
Test factoring: focusing test suites for the task at hand
477
Test fast kicker pulser
478
Test feature classifiers: performance and application
479
Test feature classifiers: performance and applications
480
Test features of a core-based co-processor array for video applications
481
Test features of the HP PA7100LC processor
482
Test features of the MC145472 ISDN U-transceivers
483
Test feeder analysis with two large induction generators using initialization and time-domain simulation
484
Test field for LV distribution systems
485
Test firmware architecture for a flexible wireless physiological multi-sensor
486
Test fixture design and shielded screening attenuation performance of CATV coaxial cable
487
Test Fixture Variance and Reliability
488
Test Fixtures for RF Susceptibility Testing
489
Test flights of GNSS1 at high latitudes
490
Test floor verification of multiprocessor hardware
491
Test Flying the World´s Fastest Airplane
492
Test for 1-D Born inversion data
493
Test for designability-a new architecture for VLSI testers
494
Test for detecting self-trapping in optical beams
495
Test for detection and location of intermittent faults in combinational circuits
496
Test for end connection integrity of metalized film capacitors
497
Test for error of current transformer based on low-voltage extrapolation method
498
Test for exogeneity of the exchange rate of RMB: HER-Johansen approach
499
Test for low cost CMOS image sensors
500
Test for Lyapunov stability by rational operations
501
Test for more than pass/fail using on-chip temperature sensor
502
Test for nonnegativity of polynomials with literal coefficients by quantifier elimination
503
Test for Planarity of a Circuit Given by an Expression
504
Test for series connected circuit breakers
505
Test for series-connected circuit breakers
506
Test for Success: Next Generation Aircraft Identification System RF Simulation
507
Test for synchronizability of finite automata and variable length codes
508
Test for the stability of polynomial matrices
509
Test for the time independence of the fine structure constant, /spl alpha/, using cryogenic sapphire resonators at microwave frequencies
510
Test for two-variable local positivity with applications
511
Test for valve controlled lead acid batteries, carried out in the battery test laboratories of DeTeImmobilien in Steinfurt Germany
512
Test forensics: A guide to evaluating TPS transportability
513
Test forensics: A guide to evaluating TPS transportability
514
Test formalism in relational diagnosis - a possibilistic approach
515
Test framework for IPv6 conformance testing
516
Test Framework Generation for Model-Based Testing in Embedded Systems
517
Test frequency selection for band-pass filters
518
Test frequency selection for overdetermined system of fault equations
519
Test frequency selection using efficient space coordinate transformation
520
Test front loading in early stages of automotive software development based on AUTOSAR
521
Test function embedding algorithms with application to interconnected finite state machines
522
Test function embedding algorithms with application to interconnected finite state machines
523
Test function specification in synthesis
524
Test generation algorithm for incomplete scan design circuits with tri-state devices
525
Test generation algorithms
526
Test Generation Algorithms for Computer Hardware Description Languages
527
Test Generation and Computational Complexity
528
TEST GENERATION AND CONCURIPENT ERROR DETECTION IN CURRENT-MODE A/D CONVERTERS
529
Test generation and concurrent error detection in current-mode A/D converters
530
Test generation and design for test for a large multiprocessing DSP
531
Test generation and design-for-testability for flow-based mVLSI microfluidic biochips
532
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines
533
Test Generation and Evaluation from High-Level Properties for Common Criteria Evaluations -- The TASCCC Testing Tool
534
Test generation and execution for security rules in temporal logic
535
Test generation and fault detection techniques in mixed circuits
536
Test generation and fault localization for quantum circuits
537
Test generation and fault modeling for stress testing
538
Test generation and fault simulation algorithms for sequential circuits with embedded RAMs
539
Test generation and fault simulation methods on the basis of cubic algebra for digital devices
540
Test generation and logic/fault simulation of programmable logic arrays: optimized partitioning techniques for parallel processing
541
Test generation and optimization for DRAM cell defects using electrical simulation
542
Test generation and scheduling for layout-based detection of bridge faults in interconnects
543
Test Generation and Site of Fault for Combinational Circuits Using Logic Petri Nets
544
Test generation and testability alternatives exploration of critical algorithms for embedded applications
545
Test generation and three-state elements, buses, and bidirectionals
546
Test generation and verification for highly sequential circuits
547
Test Generation Approach for Post-Silicon Validation of High End Microprocessor
548
Test generation at the transistor level for MOS VLSI combinational logic circuits
549
Test generation based diagnosis of device parameters for analog circuits
550
Test Generation Based on Abstraction and Test Purposes to Complement Structural Tests
551
Test generation based on dynamic search space reductions
552
Test Generation Based on Notated Net
553
Test Generation Based on SVM for Analog System with a Multi-training Sets Method
554
Test generation based on synthesizable VHDL descriptions
555
Test generation by fault sampling
556
Test generation by Lagrange programming neural network
557
Test Generation by Using Component Composition Abstraction Refinement
558
Test Generation Costs Analysis and Projections
559
Test generation for (sequential) multi-valued logic networks based on genetic algorithm
560
Test generation for IDDQ testing and leakage fault detection in CMOS circuits
561
Test generation for accurate prediction of analog specifications
562
Test generation for acyclic sequential circuits with hold registers
563
Test generation for acyclic sequential circuits with single stuck-at fault combinational ATPG
564
Test generation for analog circuits using partial numerical simulation
565
Test generation for BiCMOS circuits
566
Test generation for BiCMOS circuits
567
Test generation for Boolean expressions
568
Test Generation For Bridging Faults In CMOS ICs Based On Current Monitoring Versus Signal Propagation
569
Test generation for circuits with embedded memories using SMT
570
Test generation for clock-domain crossing faults in integrated circuits
571
Test Generation for CMP Designs
572
Test generation for combinational circuits based on DNA computing
573
Test generation for combinational circuits with multiple faults
574
Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits
575
Test generation for comprehensive testing of linear analog circuits using transient response sampling
576
Test generation for crosstalk effects in VLSI circuits
577
Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects
578
Test generation for crosstalk-induced delay in integrated circuits
579
Test generation for crosstalk-induced faults: framework and computational results
580
Test generation for C-testable one-dimensional CMOS ILA´s without observable vertical outputs
581
Test generation for current testing
582
Test generation for current testing (CMOS ICs)
583
Test generation for current testing of bridging faults in CMOS VLSI circuits
584
Test generation for cyclic combinational circuits
585
Test generation for cyclic combinational circuits
586
Test generation for data-path logic: the F-path method
587
Test generation for delay faults in non-scan and partial scan sequential circuits
588
Test generation for designs with multiple clocks
589
Test Generation for Designs with On-Chip Clock Generators
590
Test generation for digital circuits described by means of register transfer languages
591
Test generation for digital device on FPGA, CPLD
592
Test generation for double stuck-at faults
593
Test generation for E-beam testing of VLSI circuits
594
Test generation for EFSM models of complex army protocols with inconsistencies
595
Test generation for embedded circuits under the transparent-scan approach
596
Test Generation for Embedded Executables via Concolic Execution in a Real Environment
597
Test generation for fault isolation in analog circuits using behavioral models
598
Test generation for gate level sequential machines: algorithms and implementation issues
599
Test generation for gate oxide short in CMOS ICs
600
Test generation for gigahertz processors using an automatic functional constraint extractor
601
Test generation for global delay faults
602
Test generation for ground bounce in internal logic circuitry
603
Test generation for hardware-software covalidation using non-linear programming
604
Test generation for highly sequential circuits
605
Test generation for hybrid iterative logic arrays
606
Test generation for IDDQ testing of bridging faults in CMOS circuits
607
Test Generation for Interconnect Opens
608
Test generation for iterative logic arrays based on an N-cube of cell states model
609
Test generation for large automotive models
610
Test generation for linear analog circuits
611
Test generation for linear time-invariant analog circuits
612
Test generation for logic simulation based on functional graph
613
Test Generation for LSI: A Case Study
614
Test generation for maximizing ground bounce considering circuit delay
615
Test generation for maximizing ground bounce for internal circuitry with reconvergent fan-outs
616
Test Generation for Microprocessors
617
Test generation for mixed-signal devices using signal flow graphs
618
Test generation for model based fieldbus profiles
619
Test Generation for MOS Circuits Using D-Algorithm
620
Test generation for multiple faults based on parallel vector pair analysis
621
Test generation for multiple state-table faults in finite-state machines
622
Test generation for multiple state-table faults in finite-state machines
623
Test generation for multiple stuck-open faults in CMOS logic circuits
624
Test generation for multiple-threshold gate-delay fault model
625
Test generation for networks of interacting FSMs using symbolic techniques
626
Test generation for non-separable RTL controller-datapath circuits using a satisfiability based approach
627
Test Generation for Open Defects in CMOS Circuits
628
Test generation for path delay faults based on learning
629
Test generation for path delay faults using binary decision diagrams
630
Test generation for path-delay faults in one-dimensional iterative logic arrays
631
Test generation for pattern-sensitive faults in integrated switches
632
Test Generation for Precise Interrupts on Out-of-Order Microprocessors
633
Test generation for presettable synchronous sequential circuits
634
Test generation for primitive path delay faults in combinational circuits
635
Test Generation for Programmable Logic Arrays
636
Test generation for redundant faults in combinational circuits by using delay effects
637
Test Generation for Robotized Paint Systems Using Constraint Programming in a Continuous Integration Environment
638
Test Generation for RTES from SysML Models: Context, Motivations and Research Proposal
639
Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals
640
Test generation for sequential circuits
641
Test generation for sequential circuits using individual initial value propagation
642
Test generation for sequential networks affected by reconvergent fanout: a solution based on a 9-valued algebraic circuit model
643
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs
644
Test Generation for State Retention Logic
645
Test generation for stuck-at and gate-delay faults in sequential circuits: a mixed functional/structural method
646
Test generation for stuck-on faults in BDD-based pass-transistor logic SPL
647
Test generation for subtractive specification errors
648
Test generation for synchronous sequential circuits based on fault extraction
649
Test generation for synchronous sequential circuits to reduce storage requirements
650
TEST GENERATION FOR SYNCHRONOUS SEQUENTIAL CIRCUITS USING MULTIPLE OBSERVATION TIMES
651
Test generation for synchronous sequential circuits using multiple observation times
652
Test generation for technology-specific faults in multi-output combinational modules
653
Test generation for the distributed test architecture
654
Test generation for time critical systems: Tool and case study
655
Test Generation for Timing-Critical Transition Faults
656
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator
657
Test generation for ultra-high-speed asynchronous pipelines
658
Test generation for ultra-large circuits using ATPG constraints and test-pattern templates
659
Test Generation for Weak Resistive Bridges
660
Test Generation for Web Applications Using Model-Checking
661
Test Generation for X-machines with Non-terminal States and Priorities of Operations
662
Test Generation from Business Rules
663
Test generation from LOTOS specifications
664
Test Generation from Security Policies Specified in Or-BAC
665
Test generation from StateChart and B method for flight control software of unmanned aerial vehicle
666
Test generation from timed pushdown automata with inputs and outputs
667
Test Generation from UML Sequence Diagrams
668
Test generation games from formal specifications
669
Test generation in a distributed environment
670
Test generation in a parallel processing environment
671
Test generation in circuits constructed by input decomposition
672
Test Generation in Systolic Architecture for Multiplication Over GF(2 ^{m})
673
Test Generation in the Presence of Timing Exceptions and Constraints
674
Test generation in VLSI circuits for crosstalk noise
675
Test generation methodology for high-speed floating point adders
676
Test generation of analog switched-current circuits
677
Test generation of controllers using the synthesis specifications
678
Test generation of C-testable array dividers
679
Test generation of C-testable array dividers
680
Test generation of FSM with weighted transitions
681
Test Generation of Path Delay Faults Induced by Defects in Power TSV
682
Test generation strategies to measure worst-case execution time
683
Test Generation Techniques
684
Test generation techniques for sequential circuits
685
Test generation through programming in UDITA
686
Test generation to minimize error masking
687
Test generation using cross-observability calculations
688
Test Generation Using Model Checking and Specification Mutation
689
Test generation via Dynamic Symbolic Execution for mutation testing
690
Test Generation with Context Free Grammars and Covering Arrays
691
Test Generation with DHT Networks
692
Test generation with dynamic probe points in high observability testing environment
693
Test generation with high coverages for quiescent current test of bridging faults in combinational circuits
694
Test generation within an expert system environment
695
Test generation: A boundary scan implementation for module interconnect testing
696
Test Generator for Horizontal Scanning AFC System
697
Test generator with preselected toggling for low power built-in self-test
698
Test generators need to be modified to handle CMOS designs
699
Test geometry influence on antennas used for MIL-STD-461/462 testing
700
TEST GRADING THE 68332
701
Test hardware design challenges in RF testing
702
Test Harness on a Preconditioned Conjugate Gradient Solver on GPUs: An Efficiency Analysis
703
Test head design using electrooptic receivers and GaAs pin electronics for a gigahertz production test system
704
Test head scheduling in a semiconductor test facility
705
Test image generation using segmental symbolic evaluation for unit testing
706
Test implementation of a sensor device for measuring soil macronutrients
707
Test implementation to evaluate technologies for safe lunar landing
708
Test implications of lead-free implementation in a high-volume manufacturing environment
709
Test in liquid argon of the light readout system for the ArDM experiment
710
Test in the emerging intellectual property business
711
Test in the era of "What you see is not what you get" - Keynote address
712
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
713
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
714
Test infrastructure design for the Nexperia™ home platform PNX8550 system chip
715
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints
716
Test infrastructures evaluation at transaction level
717
Test input generation for supply current testing of bridging faults in bipolar combinational logic circuits
718
Test Input Generation Using UML Sequence and State Machines Models
719
Test input vectors for supply current testing of TTL combinational circuits
720
Test insertion at the RT level using functional test metrics
721
Test Inspected Unit or Inspect Unit Tested Code?
722
Test instance generation for promised NP search problems
723
Test instruction set (TIS) for high level self-testing of CPU cores
724
Test Instrumentation and Pattern Matching for Automatic Failure Identification
725
Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices
726
Test Instruments for Color Television
727
Test Instruments for Fiber Transmission Systems
728
Test instruments for radiation hazard monitoring
729
Test instruments?digital or analogue?
730
Test Integration for SOC Supporting Very Low-Cost Testers
731
Test intellectual property trends, test issues and the wealth of owning test in-house
732
Test investigation of the influence of injection rate shaping on the spray characteristics in high-pressure common rail system
733
Test Isolation Policy for Safe Runtime Validation of Evolvable Software Systems
734
Test jigs and measurements for the scanning antenna system of the multifrequency imaging microwave radiometer MIMR
735
Test laboratory position for expression of uncertainty and confidence in measurement
736
Test Length for Pseudorandom Testing
737
Test length for random testing of sequential machines application to RAMs
738
Test Length in a Self-Testing Environment
739
Test length reduction for accumulator-based self-test
740
Test Like You Fly [spacecraft]
741
Test limitations of parametric faults in analog circuits
742
Test limitations of parametric faults in analog circuits
743
Test Line Experience with HVDC Overhead Transmission
744
Test Loadability of Power Systems using A Networked Power Electronic Devices Control and Measurement System
745
Test logic reuse through unit test patterns a test automation framework for software product lines
746
Test Machine Scheduling and Optimization for z/ OS
747
Test Management
748
Test Management and Control
749
Test management and test execution system for automated verification of digital television systems
750
Test Management Framework for Managing IT Projects in Industry
751
Test management requirements for software dependent systems
752
Test management with Testopia — missing link?
753
Test Manager: A regression testing tool
754
Test manager: the test automation component for the maintenance of large-scale systems
755
Test Markup Language (TML)
756
Test masks for micromachining silicon
757
Test means at airbus military: Covering the aircraft test life-cycle with a common and standard approach
758
Test measurements considerations for LTE as future public safety communication technology
759
Test measurements of improved UWB localization technique for precision automobile parking
760
Test Men, Experts, Brother Engineers, and Members of the Fraternity: Whence the Early Electrical Work Force?
761
Test Method and Equivalent Circuit Modeling of a PEM Fuel Cell in a Passive State
762
Test method by each part for wireless transmitter and receiver system
763
Test method evaluation experiments and data
764
Test method for availability of holes in height - temperature barrier on cementation process
765
Test method for capacitive MEMS devices utilizing pierce oscillator
766
Test method for contact safety assessment of a wearable robot -analysis of load caused by a misalignment of the knee joint-
767
Test method for determination of free glycerol in Biodiesel by HPLC
768
Test method for determining the Assured Residual Life Span (ARELIS) of polyester mooring ropes
769
Test method for energy consumption of hybrid compression garbage truck
770
Test Method for Evaluation of the Resistance of Fiberglass Rods to Combined Mechanical and Chemical Stress
771
Test Method for Evaluation of the Resistance of Fiberglass Rods to Combined Mechanical and Chemical Stress
772
Test method for experimental verification of subharmonics in PWM controlled voltage source converters
773
Test Method for Heat to Electricity Conversion Efficiency of Thermoelectric Unicouple
774
Test method for IC electrical overstress hardness estimation
775
Test Method for In Situ Electrostatic Characterization of Lunar Dust
776
Test Method for Measuring Bit Error Rate of Pulsed Transceivers in Presence of Narrowband Interferers
777
Test Method for Stability Time of Electromagnetic Relay Used in Aerospace
778
Test method for the vibration response of a vehicle horn bracket
779
Test method for transformer differential relays based on symmetrical sequence components
780
Test method of composite insulators aged in high voltage rain chamber
781
Test method of field of view for terahertz imaging system
782
Test method of phased arc array for azimuthally acoustic logging tool
783
Test Method of Pneumatic Cylinder´s life
784
Test method of power and packet loss rate in smart home
785
Test method of suspender tensioning force of suspender arch bridges based on vibration test
786
Test method on precision of the 3D laser scanner
787
Test method recommendations for the evaluation of packaging materials used for small static sensitive electronic components
788
Test Method Research of Magnetic Saturation Current of High-Frequency Transformer
789
Test method research of rape adhesion properties based on image technology
790
Test method research of wet grip performance of C1 tire
791
Test Method to Demonstrate the Seismic Capabilities of Equipment
792
Test methodologies for Active Antenna System
793
Test methodologies for detecting ESD events in automated processing equipment
794
Test Methodologies for Evaluating Digital Signal Performance on Cable and Alternate Media
795
Test methodologies in the deep submicron era - analog, mixed-signal and RF
796
Test methodology for a microprocessor with partial scan
797
Test methodology for characterizing the SEE response of a commercial IEEE 1394 serial bus (FireWire)
798
Test methodology for embedded cores which protects intellectual property
799
Test methodology for evaluation of linearity of multibeam echosounder backscatter performance
800
Test methodology for Freescale´s high performance e600 core based on PowerPC/spl reg/ instruction set architecture
801
Test methodology for impedance characterization of a low voltage power line channel for broadband communication applications
802
Test methodology for low power SRAM´s (Is Iddq test useful for low power SRAM´s?)
803
Test methodology for low power VLSI neural oscillator circuit
804
Test methodology for Motorola´s high performance e500 core based on PowerPC instruction set architecture
805
Test methodology for the EMI evaluation of telephones and review of TEC standard No.S/EMI-0.1/01.Oct 94
806
Test methodology for the geostar correlator
807
Test methodology for the McKinley processor
808
Test methodology of Cu wire bond on aluminum metallization to secure good reliability
809
Test methods and application considerations for evaluation of silicone RTV coatings in the mitigation of wildlife-induced flashovers
810
Test methods and ICs for high-speed serdes
811
Test methods and influencing factors for the adhesion strength measurement of metallized structures on thermoplastic substrates
812
Test methods and results for recent outdoor insulation in Japan
813
Test methods and test equipment for surges and transients
814
Test methods and test equipment for thermal imagers
815
Test Methods and Tools for ERP Implementations
816
Test methods for armature windings
817
Test Methods for Characterizing the Local Plastic Deformability of Bonding Wires
818
Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols
819
Test methods for electrical apparatus installed on dust environments with a risk of explosion
820
Test methods for electromagnetic shielding materials
821
Test methods for polymeric insulating materials for outdoor HV insulation
822
Test methods for RF-based electronic safety equipment: Part 1 – From field tests to performance metrics
823
Test methods for RF-based electronic safety equipment: Part 2 — Development of laboratory-based tests
824
Test Methods for Stability of Digital Camera System
825
Test methods for whole vehicle radiated susceptibility
826
Test Methods of Rotating Machines
827
Test methods of the AUTOSAR application software components
828
Test methods used in fpga implementation of automatic identification system
829
Test methods used to produce highly reliable known good die (KGD)
830
Test Methods Useful in Determining the Wet Voltage Capability of Polymer Insulator Systems after Lime Related Outdoor Exposures
831
Test methods useful in selecting materials for outdoor high voltage insulation
832
Test methods, test techniques and failure criteria for evaluation of ESD degradation of analog and radio frequency (RF) technology
833
Test metric assessment of microfluidic systems through heterogeneous fault simulation
834
Test metrics for analog parametric faults
835
Test Metrics Model for Analog Test Development
836
Test minimization technique for multiple stuck-at faults of combinational circuit
837
Test Mode Entry and Exit Methods for IEEE P1581 compliant devices
838
Test mode method and strategy for RF-based fault injection analysis for on-chip relaxation oscillators under EMC standard tests or RFI susceptibility characterization
839
Test model for summarizing hindi text using extraction method
840
Test modeling and parameter identification of a gun magnetorheological recoil damper
841
Test modification and compression technique for reducing total test volume with dictionary data
842
Test modulator of AGS injection fast kicker
843
Test module of a software system for simulation study of convolutional encoders and decoders using MATLAB
844
Test module temperature measurements were made
845
Test nonlinear determinacy of Electromyogram
846
Test object reuse: a technology demonstration
847
Test of 1 m long model magnets for LHC
848
Test of 2.5 GHz WiMAX performances for business and SOHO in a multi-service environment
849
Test of 24 strip line radiation detector based on semi-insulating GaAs using X-ray source
850
Test of 3D stacked microwave TR modules
851
Test of 700MHz, 1MW proto-type klystron for PEFP
852
Test of a ß ≃ 0.1 superconducting split ring resonator
853
Test of a 1 kA superconducting fault current limiter for DC applications
854
Test of a 10 kA HTS Current Lead for ITER
855
Test of a 15,000-kw. Steam-Engine-Turbine Unit
856
Test of a 15,000-kw. steam-engine-turbine unit
857
Test of a 1500 W Fuel Cell at Practical Condition as a Source of Back-up Power in an UPS-System
858
Test of a 3”×3” LaCl3:Ce crystal and neutron sensitivity of lanthanum halide scintillators
859
Test of a 300-Kilowatt Direct-Connected Railway Unit at Different Loads
860
Test of a 622 MHz hybrid module for ATM network using a 200 MHz validation station
861
Test of a BaF2-TMAE Detector for Positron-Emission Tomography
862
Test of a bond-correction formula for ultrasonic velocity measurement
863
Test of a bouncer modulator with pulse cable at flash
864
Test of a Closed-Coil Arc Dynamo
865
Test of A CNT gyroscope based on field emission
866
Test of a compton imaging prototype at the ELBE bremsstrahlung beam
867
Test of a Compton telescope prototype based on continuous LaBr3 crystals and silicon photomultipliers
868
Test of a conceptual prototype of the total internal reflection Cherenkov imaging detector (DIRC) with cosmic muons
869
Test of a Conduction-Cooled, Prototype, Superconducting Magnet for a Compact Cyclotron
870
Test of a customized compliant ankle rehabilitation device in unpowered mode
871
Test of a double-sided double-metal silicon microstrip detector with an ONO insulator
872
Test of a fiber Bragg grating sensor network for commercial aircraft structures
873
Test of a forced-flow cooled 30 kA/23 kV current lead for the POLO model coil
874
Test of a fully integrated CMOS preamplifier for HPGe detectors
875
Test of a GEM detector in the PHENIX experiment at RHIC
876
Test of a high efficiency relativistic magnetron with diffraction output (MDO) and spherical cathode endcap
877
Test of a high T/sub c/ superconducting power transformer
878
Test of a high-field bend magnet for the ALS
879
Test of a large volume calorimeter in KEPRI tritium laboratory
880
Test of a Large-Volume Calorimeter in KEPRI Tritium Laboratory
881
Test of a LTT thyristor valve for next generation 500 kV HVDC transmission system
882
Test of a majority-based reversible (quantum) 4 bits ripple-carry adder in adiabatic calculation
883
Test of a model coil of "Tore Supra"
884
Test of a model superconducting magnet for the HERA ep interaction regions
885
Test of a Modular Fault Current Limiter for 220 V Line Using YBCO Coated Conductor Tapes With Shunt Protection
886
Test of a Nb thin film superconducting detector
887
Test of a Nb thin film superconducting detector
888
Test of a NbTi Superconducting Quadrupole Magnet Based on Alternating Helical Windings
889
Test of a prototype neutron spectrometer based on diamond detectors in a fast reactor
890
Test of a radio-frequency quadrupole cold model
891
Test of a Robust ZMP Based Pattern Generator with a 12-Internal-DoF Biped Robot Model
892
Test of a single stage 1-MV prototype induction voltage cavity
893
Test of a space cold atom clock prototype in absence of gravity
894
Test of a space cold atom clock prototype in the absence of gravity
895
Test of a Twin Coil HTS SMES for High Power Pulse Operation
896
Test of accuracy of the generalized boundary conditions in the scattering by thin dielectric strips
897
Test of amorphous metal magnetic cores using a short pulse generator
898
Test of an advanced algorithm to retrieve complex wind fields over the black sea from Envisat SAR images
899
Test of an artificial aerial telephone line at a frequency of 750 cycles per second
900
Test of an Artificial Aerial Telephone Line at a Frequency of 750 Cycles Per Second
901
Test of an Electromagnetic Shimming Concept for Superconducting Undulators
902
Test of an high data rate acoustic link in shallow water
903
Test of an induction motor with HTS wire at end ring and bars
904
Test of an Inverse Electrocardiographic Solution Based on Accurately Determined Model Data
905
Test of an optical transition radiation detector for high-intensity proton beams at FNAL
906
Test of anti-islanding protections according to IEC 62116: An experimental feasibility assessment
907
Test of applying bio-diesel in the diesel engine and prospects analysis
908
Test of Asymmetry Effect of Demand on Spot Price Using MCMC Methods
909
Test of attitude control maneuvers with a Satellite Formation Flight testbed
910
Test of base vibration influence on dynamics of a magnetic suspended disk
911
Test of BESIII Detector Magnet
912
Test of bridging faults in scan-based sequential circuits
913
Test of CMOS circuits based on its energy consumption
914
Test of Co-Movement between Electricity Consumption and Economic Growth in China
915
Test of Conductive Carbon Fiber Enhancing the Structural Bearing Capacity
916
Test of convex directions for robust stability
917
Test of correlation between GTEM cell and open area test site emission measurements
918
Test of CZT detectors with different pixel pitches and thicknesses
919
Test of data retention faults in CMOS SRAMs using special DFT circuitries
920
Test of DC reactor type fault current limiter using SMES magnet for optimal design
921
Test of different classification methodologies for land cover mapping over France using SPOT/VEGETATION data: applications to the years 2002 and 2003
922
Test of directional photoionisation models of second harmonic generation in optical fibres
923
Test of distributed data quality monitoring of CMS tracker
924
Test of duoplasmatron with cold cathode for cw operation
925
Test of eight superconducting arc quadrupoles for RHIC
926
Test of embedded analog circuits based on a built-in current sensor
927
Test of Embedded Content Addressable Memories
928
Test of EMG-720 explosive magneto-cumulative generator
929
Test of equi-scattering mechanisms for POLInSAR applications with TanDEM-X
930
Test of fast SCRs as spark gap replacement
931
Test of fast-digital beamline feedback control at the photon factory
932
Test of fault tolerant distributed systems by fault injection
933
Test of fiber-reinforced type of Nb3Sn superconducting coils
934
Test of friction loss for curved prestressed tendons
935
Test of future system-on-chips
936
Test of glass electrical solidity for high - temperature protective layers
937
Test of goodness of fit of impulse response model
938
Test of HF (3-30 MHz) MIMO communication system based on polarisation diversity
939
Test of HF ground wave radar OSMAR2000 at the Eastern China Sea
940
Test of higher-order nonlinearity via low-order harmonic generation revisited
941
Test of HTS Tapes Cooled by Liquid Nitrogen at Overloading Conditions
942
Test of IGBT Junction-Case Steady State Thermal Resistance and Experimental Analysis
943
Test of independence for cooperative spectrum sensing with uncalibrated receivers
944
Test of Information Technology (IT) - Self Efficacy and Online Learning Interaction Components on Student Retention: A Study of Synchronous Learning Environment
945
Test of interconnection opens considering coupling signals
946
Test of ionization level of rubber-insulated cables
947
Test of iron losses due to armature field for permanent magnet brushless DC motor
948
Test of iterative solvers on ITBL
949
Test of KSTAR ICRF components for long-pulse operation
950
Test of LAAPDs Coupled to CsI(Tl) Crystals for the CALIFA R3B/FAIR Calorimeter
951
Test of label-free Nasopharyngeal carinoma tissue at different stages by Raman spectroscopy
952
Test of LASL Ion Source with 200-kV Pierce Accrelerating Column
953
Test of Lead Glass Shower Counters
954
Test of Maximum Endurable Quenching Voltage of YBCO-Coated Conductors for Resistive Superconducting Fault Current Limiter
955
Test of McWhorter´s model of low-frequency noise in Si m.o.s.t.s
956
Test of metal corrosion by methanol and methanol-gasoline
957
Test of Monolithic Microwave Integrated Circuits with Radiating Probes
958
Test of New Accelerator Superconducting Dipoles Suitable for High Precision Field
959
Test of new control strategies for room temperature control systems fully controllable surroundings for a heating system with radiators
960
Test of optics diagnostics in ATF
961
Test of Optimized 120-mm LARP \\hbox {Nb}_{3}\\hbox {Sn} Quadrupole Coil Using Magnetic Mirror Structure
962
Test of Ordered Hypothesis: The Normal Variances Case
963
Test of Page-Hinckley, an approach for fault detection in an agro-alimentary production system
964
Test of Peltier Current Lead for Cryogen-Free Superconducting Magnet
965
Test of phase interpolators in high speed I/Os using a sliding window search
966
Test of phase-retrieval holography on the Onsala 20 m radiotelescope
967
Test of pitch extraction algorithms for query-by-singing/humming system
968
Test of post-fire bearing capacity of ceramsite concrete filled steel columns after exposure to fire
969
Test of post-fire bearing capacity of the circular steel tube with different coating
970
Test of preemptive real-time systems
971
Test of PWM power electronics devices for electricity network using digital real-time simulator
972
Test of RAM-based FPGA: methodology and application to the interconnect
973
Test of REBCO HTS Magnet of Magnetic Bearing for Flywheel Storage System in Solar Power System
974
Test of Resonance-Type Superconducting Fault Current Limiter
975
Test of scintillator readout with single photon avalanche photodiodes
976
Test of scintillator readout with single photon avalanche photodiodes
977
Test of SEU algorithms against preliminary CRRES satellite data
978
Test of Short Mockups for Optimization of Superconducting Undulator Coils
979
Test of SiC-electrodes in a high current pseudospark switch
980
Test of silicon hybrid pixel detector in 15 GeV electron beam
981
Test of silicon hybrid pixel detector in 15-GeV electron beam
982
Test of silicones for shipboard use
983
Test of Six High Temperature Neutron Detectors to 650°C
984
Test of spatial resolution and trigger efficiency of a combined Thin Gap and fast Drift Tube Chambers for high-luminosity LHC upgrades
985
Test of Special Relativity in a Heavy Ion Storage Ring
986
Test of subranging A/D converters with digital correction
987
Test of Superconducting Coils for the Wendelstein 7-X Stellarator Experiment
988
Test of Surface Electrical Failure of Organic Insulators by Means of Intermittent Discharges from a Capacitor
989
Test of terahertz Extended Interaction oscillator
990
Test of the Δ E/E silicon microdosimeter at the CATANA facility
991
Test of the Dynamic Characteristics of Temperature Sensor Based on Modulated Laser Driving Method
992
Test of the electron hose instability in the E157 experiment
993
Test of the ENEA Joint With a NbTi Large CiC Conductor
994
Test of the European Joint Research Centre performance model for c-Si PV modules
995
Test of the GA 12 T model coil at 4.2 K and with helium II
996
Test of the generalizability of Altman´s bankruptcy predication model
997
Test of the High-Field \\hbox {Nb}_{3}\\hbox {Sn} Dipole Magnet HD3b
998
Test of the HISPET prototype
999
Test of the hybrid robot WHEELEG on a volcanic environment
1000
Test of the ITER central solenoid model coil and CS insert